From d48b8a2bc111d30ebafdd2c661e9c0789f5c66a7 Mon Sep 17 00:00:00 2001 From: Vladimir Kostyukov Date: Tue, 24 Jun 2014 16:40:19 +0700 Subject: [PATCH] ART: FPU instructions support in disassembler This patch extends the disassembler with new FPU instructions: - fstsw - fucompp - fprem Change-Id: I9458510bc17f2b3b286edec102552f64be05147e Signed-off-by: Vladimir Kostyukov --- disassembler/disassembler_x86.cc | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc index b012bc1cc..1d8cf9b4c 100644 --- a/disassembler/disassembler_x86.cc +++ b/disassembler/disassembler_x86.cc @@ -896,6 +896,14 @@ DISASSEMBLER_ENTRY(cmp, case 0x99: opcode << "cdq"; break; + case 0x9B: + if (instr[1] == 0xDF && instr[2] == 0xE0) { + opcode << "fstsw\tax"; + instr += 2; + } else { + opcode << StringPrintf("unknown opcode '%02X'", *instr); + } + break; case 0xAF: opcode << (prefix[2] == 0x66 ? "scasw" : "scasl"); break; @@ -942,11 +950,25 @@ DISASSEMBLER_ENTRY(cmp, break; case 0xCC: opcode << "int 3"; break; case 0xD9: - static const char* d9_opcodes[] = {"flds", "unknown-d9", "fsts", "fstps", "fldenv", "fldcw", "fnstenv", "fnstcw"}; - modrm_opcodes = d9_opcodes; - store = true; - has_modrm = true; - reg_is_opcode = true; + if (instr[1] == 0xF8) { + opcode << "fprem"; + instr++; + } else { + static const char* d9_opcodes[] = {"flds", "unknown-d9", "fsts", "fstps", "fldenv", "fldcw", + "fnstenv", "fnstcw"}; + modrm_opcodes = d9_opcodes; + store = true; + has_modrm = true; + reg_is_opcode = true; + } + break; + case 0xDA: + if (instr[1] == 0xE9) { + opcode << "fucompp"; + instr++; + } else { + opcode << StringPrintf("unknown opcode '%02X'", *instr); + } break; case 0xDB: static const char* db_opcodes[] = {"fildl", "unknown-db", "unknown-db", "unknown-db", "unknown-db", "unknown-db", "unknown-db", "unknown-db"}; -- 2.11.0