From d4bcc6591812ebe72a363cf98371de5e5016f481 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 3 Oct 2012 10:03:22 -0700
Subject: [PATCH] i965/vs: Try again when we've successfully spilled a reg.

Before, we'd spill one reg, then continue on without actually register
allocating, then assertion fail when we tried to use a vgrf number as a
register number.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_vec4.h                |  4 ++--
 src/mesa/drivers/dri/i965/brw_vec4_emit.cpp         |  5 ++++-
 src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 17 ++++++++++-------
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 407e227a51d..dce3c89575d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -312,8 +312,8 @@ public:
    int setup_attributes(int payload_reg);
    int setup_uniforms(int payload_reg);
    void setup_payload();
-   void reg_allocate_trivial();
-   void reg_allocate();
+   bool reg_allocate_trivial();
+   bool reg_allocate();
    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
    int choose_spill_reg(struct ra_graph *g);
    void spill_reg(int spill_reg);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 22671f3f6ce..5a941d90c30 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -823,7 +823,10 @@ vec4_visitor::run()
       }
    }
 
-   reg_allocate();
+   while (!reg_allocate()) {
+      if (failed)
+         break;
+   }
 
    if (failed)
       return false;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 01ca6b5dc89..bad27287e5a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -41,7 +41,7 @@ assign(unsigned int *reg_hw_locations, reg *reg)
    }
 }
 
-void
+bool
 vec4_visitor::reg_allocate_trivial()
 {
    unsigned int hw_reg_mapping[this->virtual_grf_count];
@@ -90,7 +90,10 @@ vec4_visitor::reg_allocate_trivial()
    if (prog_data->total_grf > max_grf) {
       fail("Ran out of regs on trivial allocator (%d/%d)\n",
 	   prog_data->total_grf, max_grf);
+      return false;
    }
+
+   return true;
 }
 
 static void
@@ -139,7 +142,7 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
    ra_set_finalize(brw->vs.regs, NULL);
 }
 
-void
+bool
 vec4_visitor::reg_allocate()
 {
    unsigned int hw_reg_mapping[virtual_grf_count];
@@ -151,10 +154,8 @@ vec4_visitor::reg_allocate()
    /* Using the trivial allocator can be useful in debugging undefined
     * register access as a result of broken optimization passes.
     */
-   if (0) {
-      reg_allocate_trivial();
-      return;
-   }
+   if (0)
+      return reg_allocate_trivial();
 
    calculate_live_intervals();
 
@@ -213,7 +214,7 @@ vec4_visitor::reg_allocate()
          spill_reg(reg);
       }
       ralloc_free(g);
-      return;
+      return false;
    }
 
    /* Get the chosen virtual registers for each node, and map virtual
@@ -239,6 +240,8 @@ vec4_visitor::reg_allocate()
    }
 
    ralloc_free(g);
+
+   return true;
 }
 
 void
-- 
2.11.0