From d4bf52eff062ac7597c39c4d2bda40bbff1af13a Mon Sep 17 00:00:00 2001 From: astoria-d Date: Thu, 1 Aug 2013 17:56:21 +0900 Subject: [PATCH] - sty abs supported - rti supported. - test case updated. --- simulation/cpu/decoder.vhd | 71 ++++++++++++++++++++++++++ tools/test-image/sample1.asm | 116 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 187 insertions(+) diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd index 3ed5704..3d81106 100644 --- a/simulation/cpu/decoder.vhd +++ b/simulation/cpu/decoder.vhd @@ -1703,6 +1703,10 @@ end procedure; elsif instruction = conv_std_logic_vector(16#8c#, dsize) then --abs d_print("sty"); + a3_abs; + if exec_cycle = T3 then + front_oe(y_cmd, '0'); + end if; ---------------------------------------- @@ -1937,6 +1941,73 @@ end procedure; -- A.5.5 return from interrupt ---------------------------------------- elsif instruction = conv_std_logic_vector(16#40#, dsize) then + if exec_cycle = T1 then + d_print("rti 2"); + fetch_stop; + + --pop stack (decrement only) + back_oe(sp_cmd, '0'); + back_we(sp_cmd, '0'); + sp_pop_n <= '0'; + sp_oe_n <= '0'; + + next_cycle <= T2; + elsif exec_cycle = T2 then + d_print("rti 3"); + + --pop p (status) + back_oe(sp_cmd, '0'); + back_we(sp_cmd, '0'); + sp_pop_n <= '0'; + sp_oe_n <= '0'; + + --load status reg + stat_dec_oe_n <= '1'; + dbuf_int_oe_n <= '0'; + stat_bus_all_n <= '0'; + + next_cycle <= T3; + elsif exec_cycle = T3 then + d_print("rti 4"); + stat_bus_all_n <= '1'; + + --pop pcl + back_oe(sp_cmd, '0'); + back_we(sp_cmd, '0'); + sp_pop_n <= '0'; + sp_oe_n <= '0'; + + --load lo addr. + dbuf_int_oe_n <= '0'; + front_we(pcl_cmd, '0'); + + next_cycle <= T4; + elsif exec_cycle = T4 then + d_print("rti 5"); + --stack decrement stop. + back_we(sp_cmd, '1'); + sp_pop_n <= '1'; + front_we(pcl_cmd, '1'); + + --pop pch + back_oe(sp_cmd, '0'); + sp_oe_n <= '0'; + --load hi addr. + dbuf_int_oe_n <= '0'; + front_we(pch_cmd, '0'); + + next_cycle <= T5; + elsif exec_cycle = T5 then + d_print("rti 5"); + back_oe(sp_cmd, '1'); + sp_oe_n <= '1'; + --load hi addr. + dbuf_int_oe_n <= '1'; + front_we(pch_cmd, '1'); + + --increment pc. + next_cycle <= T0; + end if; --if exec_cycle = T1 then ---------------------------------------- -- A.5.6 jmp diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm index 213485b..5c17b22 100644 --- a/tools/test-image/sample1.asm +++ b/tools/test-image/sample1.asm @@ -348,6 +348,122 @@ boundary_3_4: ;;;@88fd sta $06fc, x + + ;;;;test... + STY $0720 + LDY #$80 + STY $0721 + ASL + ASL + ASL + ASL + STA $06a0 + DEC $0730 + DEC $0731 + DEC $0732 + LDA #$0b + STA $071e + ;;JSR $9c22 + LDA $0750 + ;;JSR $9c09 + AND #$60 + ASL + ROL + ROL + ROL + STA $074e + ;;RTS + TAY + LDA $0750 + AND #$1f + STA $074f + LDA $9ce0, y + CLC + ADC $074f + TAY + LDA $9ce4, y + STA $e9 + LDA $9d06, y + STA $ea + LDY $074e + LDA $9d28, y + CLC + ADC $074f + TAY + LDA $9d2c, y + STA $e7 + LDA $9d4e, y + STA $e8 + LDY #$00 + LDA ($e7), y + PHA + AND #$07 + CMP #$04 + ;;BCC +5 + STA $0741 + PLA + PHA + AND #$38 + LSR + LSR + LSR + STA $0710 + PLA + AND #$c0 + CLC + ROL + ROL + ROL + STA $0715 + INY + LDA ($e7), y + PHA + AND #$0f + STA $0727 + PLA + PHA + AND #$30 + LSR + LSR + LSR + LSR + STA $0742 + PLA + AND #$c0 + CLC + ROL + ROL + ROL + CMP #$03 + ;;BNE 5 + STA $0733 + LDA $e7 + CLC + ADC #$02 + STA $e7 + LDA $e8 + ADC #$00 + STA $e8 + ;;RTS + LDA $076a + ;;BNE 16 + LDA $075f + CMP #$04 + ;BCC 12 + LDA $075b + ;;BEQ 5 + LDA #$80 + STA $fb + LDA #$01 + STA $0774 + INC $0772 + ;;RTS + LDA $2002 + PLA + ORA #$80 + STA $2000 + rti + nop nop nop -- 2.11.0