From d826b54fdb709a886cc6c8fb548d2e1dc1d3faf2 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 19 Aug 2017 18:02:28 +0000 Subject: [PATCH] [X86] Remove an unnecessary alignment restriction from MOVDDUP pattern. The SSE MOVDDUP instruction only loads 64-bits with no alignment restriction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311253 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrSSE.td | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 6ac7ae67220..f5bc3125e18 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -5048,7 +5048,8 @@ def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))), (VMOVDDUPrm addr:$src)>; let Predicates = [UseSSE3] in { - def : Pat<(X86Movddup (memopv2f64 addr:$src)), + // No need for aligned memory as this only loads 64-bits. + def : Pat<(X86Movddup (loadv2f64 addr:$src)), (MOVDDUPrm addr:$src)>; } -- 2.11.0