From d8515652ef01afb323dbdd87499c2c950ec9d324 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Tue, 8 Oct 2013 19:06:42 +0100 Subject: [PATCH] staging: comedi: s626: prefix macros in s626.h Prefix the names of all the macros defined in "s626.h" with `S626_`. Signed-off-by: Ian Abbott Reviewed-by: H Hartley Sweeten Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/s626.c | 916 ++++++++++++++++++---------------- drivers/staging/comedi/drivers/s626.h | 721 +++++++++++++------------- 2 files changed, 842 insertions(+), 795 deletions(-) diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c index e8d615f83dee..a34e70757922 100644 --- a/drivers/staging/comedi/drivers/s626.c +++ b/drivers/staging/comedi/drivers/s626.c @@ -194,7 +194,7 @@ static bool s626_mc_test(struct comedi_device *dev, #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4) /* Write a time slot control record to TSL2. */ -#define S626_VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2)) +#define S626_VECTPORT(VECTNUM) (S626_P_TSL2 + ((VECTNUM) << 2)) static const struct comedi_lrange s626_range_table = { 2, { @@ -211,17 +211,17 @@ static void s626_debi_transfer(struct comedi_device *dev) struct s626_private *devpriv = dev->private; /* Initiate upload of shadow RAM to DEBI control register */ - s626_mc_enable(dev, MC2_UPLD_DEBI, P_MC2); + s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2); /* * Wait for completion of upload from shadow RAM to * DEBI control register. */ - while (!s626_mc_test(dev, MC2_UPLD_DEBI, P_MC2)) + while (!s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2)) ; /* Wait until DEBI transfer is done */ - while (readl(devpriv->mmio + P_PSR) & PSR_DEBI_S) + while (readl(devpriv->mmio + S626_P_PSR) & S626_PSR_DEBI_S) ; } @@ -233,12 +233,12 @@ static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr) struct s626_private *devpriv = dev->private; /* Set up DEBI control register value in shadow RAM */ - writel(DEBI_CMD_RDWORD | addr, devpriv->mmio + P_DEBICMD); + writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD); /* Execute the DEBI transfer. */ s626_debi_transfer(dev); - return readl(devpriv->mmio + P_DEBIAD); + return readl(devpriv->mmio + S626_P_DEBIAD); } /* @@ -250,8 +250,8 @@ static void s626_debi_write(struct comedi_device *dev, uint16_t addr, struct s626_private *devpriv = dev->private; /* Set up DEBI control register value in shadow RAM */ - writel(DEBI_CMD_WRWORD | addr, devpriv->mmio + P_DEBICMD); - writel(wdata, devpriv->mmio + P_DEBIAD); + writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD); + writel(wdata, devpriv->mmio + S626_P_DEBIAD); /* Execute the DEBI transfer. */ s626_debi_transfer(dev); @@ -269,14 +269,14 @@ static void s626_debi_replace(struct comedi_device *dev, unsigned int addr, unsigned int val; addr &= 0xffff; - writel(DEBI_CMD_RDWORD | addr, devpriv->mmio + P_DEBICMD); + writel(S626_DEBI_CMD_RDWORD | addr, devpriv->mmio + S626_P_DEBICMD); s626_debi_transfer(dev); - writel(DEBI_CMD_WRWORD | addr, devpriv->mmio + P_DEBICMD); - val = readl(devpriv->mmio + P_DEBIAD); + writel(S626_DEBI_CMD_WRWORD | addr, devpriv->mmio + S626_P_DEBICMD); + val = readl(devpriv->mmio + S626_P_DEBIAD); val &= mask; val |= wdata; - writel(val & 0xffff, devpriv->mmio + P_DEBIAD); + writel(val & 0xffff, devpriv->mmio + S626_P_DEBIAD); s626_debi_transfer(dev); } @@ -288,23 +288,23 @@ static uint32_t s626_i2c_handshake(struct comedi_device *dev, uint32_t val) unsigned int ctrl; /* Write I2C command to I2C Transfer Control shadow register */ - writel(val, devpriv->mmio + P_I2CCTRL); + writel(val, devpriv->mmio + S626_P_I2CCTRL); /* * Upload I2C shadow registers into working registers and * wait for upload confirmation. */ - s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2); - while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2)) + s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); + while (!s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2)) ; /* Wait until I2C bus transfer is finished or an error occurs */ do { - ctrl = readl(devpriv->mmio + P_I2CCTRL); - } while ((ctrl & (I2C_BUSY | I2C_ERR)) == I2C_BUSY); + ctrl = readl(devpriv->mmio + S626_P_I2CCTRL); + } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY); /* Return non-zero if I2C error occurred */ - return ctrl & I2C_ERR; + return ctrl & S626_I2C_ERR; } /* Read uint8_t from EEPROM. */ @@ -318,9 +318,10 @@ static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr) * Byte1 = EEPROM internal target address. * Byte0 = Not sent. */ - if (s626_i2c_handshake(dev, I2C_B2(I2C_ATTRSTART, devpriv->i2c_adrs) | - I2C_B1(I2C_ATTRSTOP, addr) | - I2C_B0(I2C_ATTRNOP, 0))) + if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, + devpriv->i2c_adrs) | + S626_I2C_B1(S626_I2C_ATTRSTOP, addr) | + S626_I2C_B0(S626_I2C_ATTRNOP, 0))) /* Abort function and declare error if handshake failed. */ return 0; @@ -330,14 +331,14 @@ static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr) * Byte1 receives uint8_t from EEPROM. * Byte0 = Not sent. */ - if (s626_i2c_handshake(dev, I2C_B2(I2C_ATTRSTART, + if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, (devpriv->i2c_adrs | 1)) | - I2C_B1(I2C_ATTRSTOP, 0) | - I2C_B0(I2C_ATTRNOP, 0))) + S626_I2C_B1(S626_I2C_ATTRSTOP, 0) | + S626_I2C_B0(S626_I2C_ATTRNOP, 0))) /* Abort function and declare error if handshake failed. */ return 0; - return (readl(devpriv->mmio + P_I2CCTRL) >> 16) & 0xff; + return (readl(devpriv->mmio + S626_P_I2CCTRL) >> 16) & 0xff; } /* *********** DAC FUNCTIONS *********** */ @@ -371,7 +372,7 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * the trailing edge of WS1/WS3 (which turns off the signals), thus * causing the signals to be inactive during the DAC write. */ - s626_debi_write(dev, LP_DACPOL, devpriv->dacpol); + s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol); /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */ @@ -385,7 +386,7 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * then immediately terminate because the protection address is * reached upon transfer of the first DWORD value. */ - s626_mc_enable(dev, MC1_A2OUT, P_MC1); + s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1); /* While the DMA transfer is executing ... */ @@ -394,7 +395,7 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * other FIFO underflow/overflow flags). When set, this flag * will indicate that we have emerged from slot 0. */ - writel(ISR_AFOU, devpriv->mmio + P_ISR); + writel(S626_ISR_AFOU, devpriv->mmio + S626_P_ISR); /* * Wait for the DMA transfer to finish so that there will be data @@ -403,7 +404,7 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * Done by polling the DMAC enable flag; this flag is automatically * cleared when the transfer has finished. */ - while (readl(devpriv->mmio + P_MC1) & MC1_A2OUT) + while (readl(devpriv->mmio + S626_P_MC1) & S626_MC1_A2OUT) ; /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */ @@ -414,7 +415,8 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list * detection. */ - writel(XSD2 | RSD3 | SIB_A2, devpriv->mmio + S626_VECTPORT(0)); + writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2, + devpriv->mmio + S626_VECTPORT(0)); /* * Wait for slot 1 to execute to ensure that the Packet will be @@ -423,7 +425,7 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * finished transferring the DAC's data DWORD from the output FIFO * to the output buffer register. */ - while (!(readl(devpriv->mmio + P_SSR) & SSR_AF2_OUT)) + while (!(readl(devpriv->mmio + S626_P_SSR) & S626_SSR_AF2_OUT)) ; /* @@ -433,7 +435,7 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * stored in the last byte to be shifted out of the FIFO's DWORD * buffer register. */ - writel(XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS, + writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS, devpriv->mmio + S626_VECTPORT(0)); /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */ @@ -456,7 +458,7 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If * the TSL has not yet finished executing slot 5 ... */ - if (readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000) { + if (readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000) { /* * The trap was set on time and we are still executing somewhere * in slots 2-5, so we now wait for slot 0 to execute and trap @@ -464,7 +466,7 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * from 0xFF to 0x00, which slot 0 causes to happen by shifting * out/in on SD2 the 0x00 that is always referenced by slot 5. */ - while (readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000) + while (readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000) ; } /* @@ -476,14 +478,15 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val) * In order to do this, we reprogram slot 0 so that it will shift in * SD3, which is driven only by a pull-up resistor. */ - writel(RSD3 | SIB_A2 | EOS, devpriv->mmio + S626_VECTPORT(0)); + writel(S626_RSD3 | S626_SIB_A2 | S626_EOS, + devpriv->mmio + S626_VECTPORT(0)); /* * Wait for slot 0 to execute, at which time the TSL is setup for * the next DAC write. This is detected when FB_BUFFER2 MSB changes * from 0x00 to 0xFF. */ - while (!(readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000)) + while (!(readl(devpriv->mmio + S626_P_FB_BUFFER2) & 0xff000000)) ; } @@ -525,15 +528,19 @@ static void s626_set_dac(struct comedi_device *dev, uint16_t chan, */ /* Choose DAC chip select to be asserted */ - ws_image = (chan & 2) ? WS1 : WS2; + ws_image = (chan & 2) ? S626_WS1 : S626_WS2; /* Slot 2: Transmit high data byte to target DAC */ - writel(XSD2 | XFIFO_1 | ws_image, devpriv->mmio + S626_VECTPORT(2)); + writel(S626_XSD2 | S626_XFIFO_1 | ws_image, + devpriv->mmio + S626_VECTPORT(2)); /* Slot 3: Transmit low data byte to target DAC */ - writel(XSD2 | XFIFO_0 | ws_image, devpriv->mmio + S626_VECTPORT(3)); + writel(S626_XSD2 | S626_XFIFO_0 | ws_image, + devpriv->mmio + S626_VECTPORT(3)); /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */ - writel(XSD2 | XFIFO_3 | WS3, devpriv->mmio + S626_VECTPORT(4)); + writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3, + devpriv->mmio + S626_VECTPORT(4)); /* Slot 5: running after writing target DAC's low data byte */ - writel(XSD2 | XFIFO_2 | WS3 | EOS, devpriv->mmio + S626_VECTPORT(5)); + writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS, + devpriv->mmio + S626_VECTPORT(5)); /* * Construct and transmit target DAC's serial packet: @@ -574,13 +581,17 @@ static void s626_write_trim_dac(struct comedi_device *dev, uint8_t logical_chan, */ /* Slot 2: Send high uint8_t to target TrimDac */ - writel(XSD2 | XFIFO_1 | WS3, devpriv->mmio + S626_VECTPORT(2)); + writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3, + devpriv->mmio + S626_VECTPORT(2)); /* Slot 3: Send low uint8_t to target TrimDac */ - writel(XSD2 | XFIFO_0 | WS3, devpriv->mmio + S626_VECTPORT(3)); + writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3, + devpriv->mmio + S626_VECTPORT(3)); /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */ - writel(XSD2 | XFIFO_3 | WS1, devpriv->mmio + S626_VECTPORT(4)); + writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1, + devpriv->mmio + S626_VECTPORT(4)); /* Slot 5: Send NOP low uint8_t to DAC0 */ - writel(XSD2 | XFIFO_2 | WS1 | EOS, devpriv->mmio + S626_VECTPORT(5)); + writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS, + devpriv->mmio + S626_VECTPORT(5)); /* * Construct and transmit target DAC's serial packet: @@ -643,8 +654,9 @@ static uint32_t s626_read_latch(struct comedi_device *dev, static void s626_set_latch_source(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t value) { - s626_debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC), - value << CRBBIT_LATCHSRC); + s626_debi_replace(dev, k->my_crb, + ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC), + value << S626_CRBBIT_LATCHSRC); } /* @@ -665,15 +677,15 @@ static void s626_preload(struct comedi_device *dev, static void s626_reset_cap_flags_a(struct comedi_device *dev, const struct s626_enc_info *k) { - s626_debi_replace(dev, k->my_crb, ~CRBMSK_INTCTRL, - CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A); + s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL, + S626_CRBMSK_INTRESETCMD | S626_CRBMSK_INTRESET_A); } static void s626_reset_cap_flags_b(struct comedi_device *dev, const struct s626_enc_info *k) { - s626_debi_replace(dev, k->my_crb, ~CRBMSK_INTCTRL, - CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B); + s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL, + S626_CRBMSK_INTRESETCMD | S626_CRBMSK_INTRESET_B); } /* @@ -695,41 +707,43 @@ static uint16_t s626_get_mode_a(struct comedi_device *dev, * Populate the standardized counter setup bit fields. * Note: IndexSrc is restricted to ENC_X or IndxPol. */ - setup = (cra & STDMSK_LOADSRC) | /* LoadSrc = LoadSrcA. */ - ((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & - STDMSK_LATCHSRC) | /* LatchSrc = LatchSrcA. */ - ((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & - STDMSK_INTSRC) | /* IntSrc = IntSrcA. */ - ((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & - STDMSK_INDXSRC) | /* IndxSrc = IndxSrcA<1>. */ - ((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & - STDMSK_INDXPOL) | /* IndxPol = IndxPolA. */ - ((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & - STDMSK_CLKENAB); /* ClkEnab = ClkEnabA. */ + setup = (cra & S626_STDMSK_LOADSRC) | /* LoadSrc = LoadSrcA. */ + ((crb << (S626_STDBIT_LATCHSRC - S626_CRBBIT_LATCHSRC)) & + S626_STDMSK_LATCHSRC) | /* LatchSrc = LatchSrcA. */ + ((cra << (S626_STDBIT_INTSRC - S626_CRABIT_INTSRC_A)) & + S626_STDMSK_INTSRC) | /* IntSrc = IntSrcA. */ + ((cra << (S626_STDBIT_INDXSRC - (S626_CRABIT_INDXSRC_A + 1))) & + S626_STDMSK_INDXSRC) | /* IndxSrc = IndxSrcA<1>. */ + ((cra >> (S626_CRABIT_INDXPOL_A - S626_STDBIT_INDXPOL)) & + S626_STDMSK_INDXPOL) | /* IndxPol = IndxPolA. */ + ((crb >> (S626_CRBBIT_CLKENAB_A - S626_STDBIT_CLKENAB)) & + S626_STDMSK_CLKENAB); /* ClkEnab = ClkEnabA. */ /* Adjust mode-dependent parameters. */ - if (cra & (2 << CRABIT_CLKSRC_A)) { + if (cra & (2 << S626_CRABIT_CLKSRC_A)) { /* Timer mode (ClkSrcA<1> == 1): */ /* Indicate Timer mode. */ - setup |= CLKSRC_TIMER << STDBIT_CLKSRC; + setup |= S626_CLKSRC_TIMER << S626_STDBIT_CLKSRC; /* Set ClkPol to indicate count direction (ClkSrcA<0>). */ - setup |= (cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & - STDMSK_CLKPOL; + setup |= (cra << (S626_STDBIT_CLKPOL - S626_CRABIT_CLKSRC_A)) & + S626_STDMSK_CLKPOL; /* ClkMult must be 1x in Timer mode. */ - setup |= MULT_X1 << STDBIT_CLKMULT; + setup |= S626_MULT_X1 << S626_STDBIT_CLKMULT; } else { /* Counter mode (ClkSrcA<1> == 0): */ /* Indicate Counter mode. */ - setup |= CLKSRC_COUNTER << STDBIT_CLKSRC; + setup |= S626_CLKSRC_COUNTER << S626_STDBIT_CLKSRC; /* Pass through ClkPol. */ - setup |= (cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & - STDMSK_CLKPOL; + setup |= (cra >> (S626_CRABIT_CLKPOL_A - S626_STDBIT_CLKPOL)) & + S626_STDMSK_CLKPOL; /* Force ClkMult to 1x if not legal, else pass through. */ - if ((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) - setup |= MULT_X1 << STDBIT_CLKMULT; + if ((cra & S626_CRAMSK_CLKMULT_A) == + (S626_MULT_X0 << S626_CRABIT_CLKMULT_A)) + setup |= S626_MULT_X1 << S626_STDBIT_CLKMULT; else - setup |= (cra >> (CRABIT_CLKMULT_A - STDBIT_CLKMULT)) & - STDMSK_CLKMULT; + setup |= (cra >> (S626_CRABIT_CLKMULT_A - + S626_STDBIT_CLKMULT)) & + S626_STDMSK_CLKMULT; } /* Return adjusted counter setup. */ @@ -751,48 +765,49 @@ static uint16_t s626_get_mode_b(struct comedi_device *dev, * Populate the standardized counter setup bit fields. * Note: IndexSrc is restricted to ENC_X or IndxPol. */ - setup = ((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & - STDMSK_INTSRC) | /* IntSrc = IntSrcB. */ - ((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & - STDMSK_LATCHSRC) | /* LatchSrc = LatchSrcB. */ - ((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & - STDMSK_LOADSRC) | /* LoadSrc = LoadSrcB. */ - ((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & - STDMSK_INDXPOL) | /* IndxPol = IndxPolB. */ - ((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & - STDMSK_CLKENAB) | /* ClkEnab = ClkEnabB. */ - ((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & - STDMSK_INDXSRC); /* IndxSrc = IndxSrcB<1>. */ + setup = ((crb << (S626_STDBIT_INTSRC - S626_CRBBIT_INTSRC_B)) & + S626_STDMSK_INTSRC) | /* IntSrc = IntSrcB. */ + ((crb << (S626_STDBIT_LATCHSRC - S626_CRBBIT_LATCHSRC)) & + S626_STDMSK_LATCHSRC) | /* LatchSrc = LatchSrcB. */ + ((crb << (S626_STDBIT_LOADSRC - S626_CRBBIT_LOADSRC_B)) & + S626_STDMSK_LOADSRC) | /* LoadSrc = LoadSrcB. */ + ((crb << (S626_STDBIT_INDXPOL - S626_CRBBIT_INDXPOL_B)) & + S626_STDMSK_INDXPOL) | /* IndxPol = IndxPolB. */ + ((crb >> (S626_CRBBIT_CLKENAB_B - S626_STDBIT_CLKENAB)) & + S626_STDMSK_CLKENAB) | /* ClkEnab = ClkEnabB. */ + ((cra >> ((S626_CRABIT_INDXSRC_B + 1) - S626_STDBIT_INDXSRC)) & + S626_STDMSK_INDXSRC); /* IndxSrc = IndxSrcB<1>. */ /* Adjust mode-dependent parameters. */ - if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) { - /* Extender mode (ClkMultB == MULT_X0): */ + if ((crb & S626_CRBMSK_CLKMULT_B) == + (S626_MULT_X0 << S626_CRBBIT_CLKMULT_B)) { + /* Extender mode (ClkMultB == S626_MULT_X0): */ /* Indicate Extender mode. */ - setup |= CLKSRC_EXTENDER << STDBIT_CLKSRC; + setup |= S626_CLKSRC_EXTENDER << S626_STDBIT_CLKSRC; /* Indicate multiplier is 1x. */ - setup |= MULT_X1 << STDBIT_CLKMULT; + setup |= S626_MULT_X1 << S626_STDBIT_CLKMULT; /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */ - setup |= (cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & - STDMSK_CLKPOL; - } else if (cra & (2 << CRABIT_CLKSRC_B)) { + setup |= (cra >> (S626_CRABIT_CLKSRC_B - S626_STDBIT_CLKPOL)) & + S626_STDMSK_CLKPOL; + } else if (cra & (2 << S626_CRABIT_CLKSRC_B)) { /* Timer mode (ClkSrcB<1> == 1): */ /* Indicate Timer mode. */ - setup |= CLKSRC_TIMER << STDBIT_CLKSRC; + setup |= S626_CLKSRC_TIMER << S626_STDBIT_CLKSRC; /* Indicate multiplier is 1x. */ - setup |= MULT_X1 << STDBIT_CLKMULT; + setup |= S626_MULT_X1 << S626_STDBIT_CLKMULT; /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */ - setup |= (cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & - STDMSK_CLKPOL; + setup |= (cra >> (S626_CRABIT_CLKSRC_B - S626_STDBIT_CLKPOL)) & + S626_STDMSK_CLKPOL; } else { /* If Counter mode (ClkSrcB<1> == 0): */ /* Indicate Timer mode. */ - setup |= CLKSRC_COUNTER << STDBIT_CLKSRC; + setup |= S626_CLKSRC_COUNTER << S626_STDBIT_CLKSRC; /* Clock multiplier is passed through. */ - setup |= (crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & - STDMSK_CLKMULT; + setup |= (crb >> (S626_CRBBIT_CLKMULT_B - + S626_STDBIT_CLKMULT)) & S626_STDMSK_CLKMULT; /* Clock polarity is passed through. */ - setup |= (crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & - STDMSK_CLKPOL; + setup |= (crb << (S626_STDBIT_CLKPOL - S626_CRBBIT_CLKPOL_B)) & + S626_STDMSK_CLKPOL; } /* Return adjusted counter setup. */ @@ -815,49 +830,51 @@ static void s626_set_mode_a(struct comedi_device *dev, /* Initialize CRA and CRB images. */ /* Preload trigger is passed through. */ - cra = setup & CRAMSK_LOADSRC_A; + cra = setup & S626_CRAMSK_LOADSRC_A; /* IndexSrc is restricted to ENC_X or IndxPol. */ - cra |= ((setup & STDMSK_INDXSRC) >> - (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))); + cra |= (setup & S626_STDMSK_INDXSRC) >> + (S626_STDBIT_INDXSRC - (S626_CRABIT_INDXSRC_A + 1)); /* Reset any pending CounterA event captures. */ - crb = CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A; + crb = S626_CRBMSK_INTRESETCMD | S626_CRBMSK_INTRESET_A; /* Clock enable is passed through. */ - crb |= (setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB); + crb |= (setup & S626_STDMSK_CLKENAB) << + (S626_CRBBIT_CLKENAB_A - S626_STDBIT_CLKENAB); /* Force IntSrc to Disabled if disable_int_src is asserted. */ if (!disable_int_src) - cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC - - CRABIT_INTSRC_A)); + cra |= (setup & S626_STDMSK_INTSRC) >> + (S626_STDBIT_INTSRC - S626_CRABIT_INTSRC_A); /* Populate all mode-dependent attributes of CRA & CRB images. */ - switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) { - case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode - * (Extender valid only for B counters). */ - /* Fall through to case CLKSRC_TIMER: */ - case CLKSRC_TIMER: /* Timer Mode: */ + switch ((setup & S626_STDMSK_CLKSRC) >> S626_STDBIT_CLKSRC) { + case S626_CLKSRC_EXTENDER: /* Extender Mode: */ + /* Force to Timer mode (Extender valid only for B counters). */ + /* Fall through to case S626_CLKSRC_TIMER: */ + case S626_CLKSRC_TIMER: /* Timer Mode: */ /* ClkSrcA<1> selects system clock */ - cra |= 2 << CRABIT_CLKSRC_A; + cra |= 2 << S626_CRABIT_CLKSRC_A; /* Count direction (ClkSrcA<0>) obtained from ClkPol. */ - cra |= (setup & STDMSK_CLKPOL) >> - (STDBIT_CLKPOL - CRABIT_CLKSRC_A); + cra |= (setup & S626_STDMSK_CLKPOL) >> + (S626_STDBIT_CLKPOL - S626_CRABIT_CLKSRC_A); /* ClkPolA behaves as always-on clock enable. */ - cra |= 1 << CRABIT_CLKPOL_A; + cra |= 1 << S626_CRABIT_CLKPOL_A; /* ClkMult must be 1x. */ - cra |= MULT_X1 << CRABIT_CLKMULT_A; + cra |= S626_MULT_X1 << S626_CRABIT_CLKMULT_A; break; default: /* Counter Mode: */ /* Select ENC_C and ENC_D as clock/direction inputs. */ - cra |= CLKSRC_COUNTER; + cra |= S626_CLKSRC_COUNTER; /* Clock polarity is passed through. */ - cra |= (setup & STDMSK_CLKPOL) << - (CRABIT_CLKPOL_A - STDBIT_CLKPOL); + cra |= (setup & S626_STDMSK_CLKPOL) << + (S626_CRABIT_CLKPOL_A - S626_STDBIT_CLKPOL); /* Force multiplier to x1 if not legal, else pass through. */ - if ((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) - cra |= MULT_X1 << CRABIT_CLKMULT_A; + if ((setup & S626_STDMSK_CLKMULT) == + (S626_MULT_X0 << S626_STDBIT_CLKMULT)) + cra |= S626_MULT_X1 << S626_CRABIT_CLKMULT_A; else - cra |= (setup & STDMSK_CLKMULT) << - (CRABIT_CLKMULT_A - STDBIT_CLKMULT); + cra |= (setup & S626_STDMSK_CLKMULT) << + (S626_CRABIT_CLKMULT_A - S626_STDBIT_CLKMULT); break; } @@ -865,9 +882,9 @@ static void s626_set_mode_a(struct comedi_device *dev, * Force positive index polarity if IndxSrc is software-driven only, * otherwise pass it through. */ - if (~setup & STDMSK_INDXSRC) - cra |= (setup & STDMSK_INDXPOL) << - (CRABIT_INDXPOL_A - STDBIT_INDXPOL); + if (~setup & S626_STDMSK_INDXSRC) + cra |= (setup & S626_STDMSK_INDXPOL) << + (S626_CRABIT_INDXPOL_A - S626_STDBIT_INDXPOL); /* * If IntSrc has been forced to Disabled, update the MISC2 interrupt @@ -880,10 +897,10 @@ static void s626_set_mode_a(struct comedi_device *dev, * While retaining CounterB and LatchSrc configurations, program the * new counter operating mode. */ - s626_debi_replace(dev, k->my_cra, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, - cra); - s626_debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A), - crb); + s626_debi_replace(dev, k->my_cra, + S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CLKSRC_B, cra); + s626_debi_replace(dev, k->my_crb, + ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb); } static void s626_set_mode_b(struct comedi_device *dev, @@ -896,57 +913,60 @@ static void s626_set_mode_b(struct comedi_device *dev, /* Initialize CRA and CRB images. */ /* IndexSrc field is restricted to ENC_X or IndxPol. */ - cra = (setup & STDMSK_INDXSRC) << - (CRABIT_INDXSRC_B + 1 - STDBIT_INDXSRC); + cra = (setup & S626_STDMSK_INDXSRC) << + (S626_CRABIT_INDXSRC_B + 1 - S626_STDBIT_INDXSRC); /* Reset event captures and disable interrupts. */ - crb = CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B; + crb = S626_CRBMSK_INTRESETCMD | S626_CRBMSK_INTRESET_B; /* Clock enable is passed through. */ - crb |= (setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB); + crb |= (setup & S626_STDMSK_CLKENAB) << + (S626_CRBBIT_CLKENAB_B - S626_STDBIT_CLKENAB); /* Preload trigger source is passed through. */ - crb |= (setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B); + crb |= (setup & S626_STDMSK_LOADSRC) >> + (S626_STDBIT_LOADSRC - S626_CRBBIT_LOADSRC_B); /* Force IntSrc to Disabled if disable_int_src is asserted. */ if (!disable_int_src) - crb |= (setup & STDMSK_INTSRC) >> - (STDBIT_INTSRC - CRBBIT_INTSRC_B); + crb |= (setup & S626_STDMSK_INTSRC) >> + (S626_STDBIT_INTSRC - S626_CRBBIT_INTSRC_B); /* Populate all mode-dependent attributes of CRA & CRB images. */ - switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) { - case CLKSRC_TIMER: /* Timer Mode: */ + switch ((setup & S626_STDMSK_CLKSRC) >> S626_STDBIT_CLKSRC) { + case S626_CLKSRC_TIMER: /* Timer Mode: */ /* ClkSrcB<1> selects system clock */ - cra |= 2 << CRABIT_CLKSRC_B; + cra |= 2 << S626_CRABIT_CLKSRC_B; /* with direction (ClkSrcB<0>) obtained from ClkPol. */ - cra |= (setup & STDMSK_CLKPOL) << - (CRABIT_CLKSRC_B - STDBIT_CLKPOL); + cra |= (setup & S626_STDMSK_CLKPOL) << + (S626_CRABIT_CLKSRC_B - S626_STDBIT_CLKPOL); /* ClkPolB behaves as always-on clock enable. */ - crb |= 1 << CRBBIT_CLKPOL_B; + crb |= 1 << S626_CRBBIT_CLKPOL_B; /* ClkMultB must be 1x. */ - crb |= MULT_X1 << CRBBIT_CLKMULT_B; + crb |= S626_MULT_X1 << S626_CRBBIT_CLKMULT_B; break; - case CLKSRC_EXTENDER: /* Extender Mode: */ + case S626_CLKSRC_EXTENDER: /* Extender Mode: */ /* ClkSrcB source is OverflowA (same as "timer") */ - cra |= 2 << CRABIT_CLKSRC_B; + cra |= 2 << S626_CRABIT_CLKSRC_B; /* with direction obtained from ClkPol. */ - cra |= (setup & STDMSK_CLKPOL) << - (CRABIT_CLKSRC_B - STDBIT_CLKPOL); + cra |= (setup & S626_STDMSK_CLKPOL) << + (S626_CRABIT_CLKSRC_B - S626_STDBIT_CLKPOL); /* ClkPolB controls IndexB -- always set to active. */ - crb |= 1 << CRBBIT_CLKPOL_B; + crb |= 1 << S626_CRBBIT_CLKPOL_B; /* ClkMultB selects OverflowA as the clock source. */ - crb |= MULT_X0 << CRBBIT_CLKMULT_B; + crb |= S626_MULT_X0 << S626_CRBBIT_CLKMULT_B; break; default: /* Counter Mode: */ /* Select ENC_C and ENC_D as clock/direction inputs. */ - cra |= CLKSRC_COUNTER << CRABIT_CLKSRC_B; + cra |= S626_CLKSRC_COUNTER << S626_CRABIT_CLKSRC_B; /* ClkPol is passed through. */ - crb |= (setup & STDMSK_CLKPOL) >> - (STDBIT_CLKPOL - CRBBIT_CLKPOL_B); + crb |= (setup & S626_STDMSK_CLKPOL) >> + (S626_STDBIT_CLKPOL - S626_CRBBIT_CLKPOL_B); /* Force ClkMult to x1 if not legal, otherwise pass through. */ - if ((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) - crb |= MULT_X1 << CRBBIT_CLKMULT_B; + if ((setup & S626_STDMSK_CLKMULT) == + (S626_MULT_X0 << S626_STDBIT_CLKMULT)) + crb |= S626_MULT_X1 << S626_CRBBIT_CLKMULT_B; else - crb |= (setup & STDMSK_CLKMULT) << - (CRBBIT_CLKMULT_B - STDBIT_CLKMULT); + crb |= (setup & S626_STDMSK_CLKMULT) << + (S626_CRBBIT_CLKMULT_B - S626_STDBIT_CLKMULT); break; } @@ -954,9 +974,9 @@ static void s626_set_mode_b(struct comedi_device *dev, * Force positive index polarity if IndxSrc is software-driven only, * otherwise pass it through. */ - if (~setup & STDMSK_INDXSRC) - crb |= (setup & STDMSK_INDXPOL) >> - (STDBIT_INDXPOL - CRBBIT_INDXPOL_B); + if (~setup & S626_STDMSK_INDXSRC) + crb |= (setup & S626_STDMSK_INDXPOL) >> + (S626_STDBIT_INDXPOL - S626_CRBBIT_INDXPOL_B); /* * If IntSrc has been forced to Disabled, update the MISC2 interrupt @@ -969,10 +989,10 @@ static void s626_set_mode_b(struct comedi_device *dev, * While retaining CounterA and LatchSrc configurations, program the * new counter operating mode. */ - s626_debi_replace(dev, k->my_cra, ~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B), - cra); - s626_debi_replace(dev, k->my_crb, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, - crb); + s626_debi_replace(dev, k->my_cra, + ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CLKSRC_B), cra); + s626_debi_replace(dev, k->my_crb, + S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb); } /* @@ -981,34 +1001,36 @@ static void s626_set_mode_b(struct comedi_device *dev, static void s626_set_enable_a(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t enab) { - s626_debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A), - enab << CRBBIT_CLKENAB_A); + s626_debi_replace(dev, k->my_crb, + ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), + enab << S626_CRBBIT_CLKENAB_A); } static void s626_set_enable_b(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t enab) { - s626_debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B), - enab << CRBBIT_CLKENAB_B); + s626_debi_replace(dev, k->my_crb, + ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_B), + enab << S626_CRBBIT_CLKENAB_B); } static uint16_t s626_get_enable_a(struct comedi_device *dev, const struct s626_enc_info *k) { - return (s626_debi_read(dev, k->my_crb) >> CRBBIT_CLKENAB_A) & 1; + return (s626_debi_read(dev, k->my_crb) >> S626_CRBBIT_CLKENAB_A) & 1; } static uint16_t s626_get_enable_b(struct comedi_device *dev, const struct s626_enc_info *k) { - return (s626_debi_read(dev, k->my_crb) >> CRBBIT_CLKENAB_B) & 1; + return (s626_debi_read(dev, k->my_crb) >> S626_CRBBIT_CLKENAB_B) & 1; } #ifdef unused static uint16_t s626_get_latch_source(struct comedi_device *dev, const struct s626_enc_info *k) { - return (s626_debi_read(dev, k->my_crb) >> CRBBIT_LATCHSRC) & 3; + return (s626_debi_read(dev, k->my_crb) >> S626_CRBBIT_LATCHSRC) & 3; } #endif @@ -1020,27 +1042,28 @@ static uint16_t s626_get_latch_source(struct comedi_device *dev, static void s626_set_load_trig_a(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t trig) { - s626_debi_replace(dev, k->my_cra, ~CRAMSK_LOADSRC_A, - trig << CRABIT_LOADSRC_A); + s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_LOADSRC_A, + trig << S626_CRABIT_LOADSRC_A); } static void s626_set_load_trig_b(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t trig) { - s626_debi_replace(dev, k->my_crb, ~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL), - trig << CRBBIT_LOADSRC_B); + s626_debi_replace(dev, k->my_crb, + ~(S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL), + trig << S626_CRBBIT_LOADSRC_B); } static uint16_t s626_get_load_trig_a(struct comedi_device *dev, const struct s626_enc_info *k) { - return (s626_debi_read(dev, k->my_cra) >> CRABIT_LOADSRC_A) & 3; + return (s626_debi_read(dev, k->my_cra) >> S626_CRABIT_LOADSRC_A) & 3; } static uint16_t s626_get_load_trig_b(struct comedi_device *dev, const struct s626_enc_info *k) { - return (s626_debi_read(dev, k->my_crb) >> CRBBIT_LOADSRC_B) & 3; + return (s626_debi_read(dev, k->my_crb) >> S626_CRBBIT_LOADSRC_B) & 3; } /* @@ -1055,12 +1078,12 @@ static void s626_set_int_src_a(struct comedi_device *dev, struct s626_private *devpriv = dev->private; /* Reset any pending counter overflow or index captures. */ - s626_debi_replace(dev, k->my_crb, ~CRBMSK_INTCTRL, - CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A); + s626_debi_replace(dev, k->my_crb, ~S626_CRBMSK_INTCTRL, + S626_CRBMSK_INTRESETCMD | S626_CRBMSK_INTRESET_A); /* Program counter interrupt source. */ - s626_debi_replace(dev, k->my_cra, ~CRAMSK_INTSRC_A, - int_source << CRABIT_INTSRC_A); + s626_debi_replace(dev, k->my_cra, ~S626_CRAMSK_INTSRC_A, + int_source << S626_CRABIT_INTSRC_A); /* Update MISC2 interrupt enable mask. */ devpriv->counter_int_enabs = @@ -1076,16 +1099,16 @@ static void s626_set_int_src_b(struct comedi_device *dev, uint16_t crb; /* Cache writeable CRB register image. */ - crb = s626_debi_read(dev, k->my_crb) & ~CRBMSK_INTCTRL; + crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL; /* Reset any pending counter overflow or index captures. */ - s626_debi_write(dev, k->my_crb, - (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B)); + s626_debi_write(dev, k->my_crb, (crb | S626_CRBMSK_INTRESETCMD | + S626_CRBMSK_INTRESET_B)); /* Program counter interrupt source. */ s626_debi_write(dev, k->my_crb, - ((crb & ~CRBMSK_INTSRC_B) | - (int_source << CRBBIT_INTSRC_B))); + ((crb & ~S626_CRBMSK_INTSRC_B) | + (int_source << S626_CRBBIT_INTSRC_B))); /* Update MISC2 interrupt enable mask. */ devpriv->counter_int_enabs = @@ -1096,13 +1119,13 @@ static void s626_set_int_src_b(struct comedi_device *dev, static uint16_t s626_get_int_src_a(struct comedi_device *dev, const struct s626_enc_info *k) { - return (s626_debi_read(dev, k->my_cra) >> CRABIT_INTSRC_A) & 3; + return (s626_debi_read(dev, k->my_cra) >> S626_CRABIT_INTSRC_A) & 3; } static uint16_t s626_get_int_src_b(struct comedi_device *dev, const struct s626_enc_info *k) { - return (s626_debi_read(dev, k->my_crb) >> CRBBIT_INTSRC_B) & 3; + return (s626_debi_read(dev, k->my_crb) >> S626_CRBBIT_INTSRC_B) & 3; } #ifdef unused @@ -1112,14 +1135,14 @@ static uint16_t s626_get_int_src_b(struct comedi_device *dev, static void s626_set_clk_mult(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t value) { - k->set_mode(dev, k, ((k->get_mode(dev, k) & ~STDMSK_CLKMULT) | - (value << STDBIT_CLKMULT)), false); + k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKMULT) | + (value << S626_STDBIT_CLKMULT)), false); } static uint16_t s626_get_clk_mult(struct comedi_device *dev, const struct s626_enc_info *k) { - return (k->get_mode(dev, k) >> STDBIT_CLKMULT) & 3; + return (k->get_mode(dev, k) >> S626_STDBIT_CLKMULT) & 3; } /* @@ -1128,14 +1151,14 @@ static uint16_t s626_get_clk_mult(struct comedi_device *dev, static void s626_set_clk_pol(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t value) { - k->set_mode(dev, k, ((k->get_mode(dev, k) & ~STDMSK_CLKPOL) | - (value << STDBIT_CLKPOL)), false); + k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKPOL) | + (value << S626_STDBIT_CLKPOL)), false); } static uint16_t s626_get_clk_pol(struct comedi_device *dev, const struct s626_enc_info *k) { - return (k->get_mode(dev, k) >> STDBIT_CLKPOL) & 1; + return (k->get_mode(dev, k) >> S626_STDBIT_CLKPOL) & 1; } /* @@ -1144,14 +1167,14 @@ static uint16_t s626_get_clk_pol(struct comedi_device *dev, static void s626_set_clk_src(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t value) { - k->set_mode(dev, k, ((k->get_mode(dev, k) & ~STDMSK_CLKSRC) | - (value << STDBIT_CLKSRC)), false); + k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKSRC) | + (value << S626_STDBIT_CLKSRC)), false); } static uint16_t s626_get_clk_src(struct comedi_device *dev, const struct s626_enc_info *k) { - return (k->get_mode(dev, k) >> STDBIT_CLKSRC) & 3; + return (k->get_mode(dev, k) >> S626_STDBIT_CLKSRC) & 3; } /* @@ -1160,14 +1183,14 @@ static uint16_t s626_get_clk_src(struct comedi_device *dev, static void s626_set_index_pol(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t value) { - k->set_mode(dev, k, ((k->get_mode(dev, k) & ~STDMSK_INDXPOL) | - ((value != 0) << STDBIT_INDXPOL)), false); + k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXPOL) | + ((value != 0) << S626_STDBIT_INDXPOL)), false); } static uint16_t s626_get_index_pol(struct comedi_device *dev, const struct s626_enc_info *k) { - return (k->get_mode(dev, k) >> STDBIT_INDXPOL) & 1; + return (k->get_mode(dev, k) >> S626_STDBIT_INDXPOL) & 1; } /* @@ -1176,14 +1199,14 @@ static uint16_t s626_get_index_pol(struct comedi_device *dev, static void s626_set_index_src(struct comedi_device *dev, const struct s626_enc_info *k, uint16_t value) { - k->set_mode(dev, k, ((k->get_mode(dev, k) & ~STDMSK_INDXSRC) | - ((value != 0) << STDBIT_INDXSRC)), false); + k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_INDXSRC) | + ((value != 0) << S626_STDBIT_INDXSRC)), false); } static uint16_t s626_get_index_src(struct comedi_device *dev, const struct s626_enc_info *k) { - return (k->get_mode(dev, k) >> STDBIT_INDXSRC) & 1; + return (k->get_mode(dev, k) >> S626_STDBIT_INDXSRC) & 1; } #endif @@ -1197,7 +1220,7 @@ static void s626_pulse_index_a(struct comedi_device *dev, cra = s626_debi_read(dev, k->my_cra); /* Pulse index. */ - s626_debi_write(dev, k->my_cra, (cra ^ CRAMSK_INDXPOL_A)); + s626_debi_write(dev, k->my_cra, (cra ^ S626_CRAMSK_INDXPOL_A)); s626_debi_write(dev, k->my_cra, cra); } @@ -1206,9 +1229,9 @@ static void s626_pulse_index_b(struct comedi_device *dev, { uint16_t crb; - crb = s626_debi_read(dev, k->my_crb) & ~CRBMSK_INTCTRL; + crb = s626_debi_read(dev, k->my_crb) & ~S626_CRBMSK_INTCTRL; /* Pulse index. */ - s626_debi_write(dev, k->my_crb, (crb ^ CRBMSK_INDXPOL_B)); + s626_debi_write(dev, k->my_crb, (crb ^ S626_CRBMSK_INDXPOL_B)); s626_debi_write(dev, k->my_crb, crb); } @@ -1224,9 +1247,9 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_a, .set_mode = s626_set_mode_a, .reset_cap_flags = s626_reset_cap_flags_a, - .my_cra = LP_CR0A, - .my_crb = LP_CR0B, - .my_latch_lsw = LP_CNTR0ALSW, + .my_cra = S626_LP_CR0A, + .my_crb = S626_LP_CR0B, + .my_latch_lsw = S626_LP_CNTR0ALSW, .my_event_bits = S626_EVBITS(0), }, { .get_enable = s626_get_enable_a, @@ -1239,9 +1262,9 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_a, .set_mode = s626_set_mode_a, .reset_cap_flags = s626_reset_cap_flags_a, - .my_cra = LP_CR1A, - .my_crb = LP_CR1B, - .my_latch_lsw = LP_CNTR1ALSW, + .my_cra = S626_LP_CR1A, + .my_crb = S626_LP_CR1B, + .my_latch_lsw = S626_LP_CNTR1ALSW, .my_event_bits = S626_EVBITS(1), }, { .get_enable = s626_get_enable_a, @@ -1254,9 +1277,9 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_a, .set_mode = s626_set_mode_a, .reset_cap_flags = s626_reset_cap_flags_a, - .my_cra = LP_CR2A, - .my_crb = LP_CR2B, - .my_latch_lsw = LP_CNTR2ALSW, + .my_cra = S626_LP_CR2A, + .my_crb = S626_LP_CR2B, + .my_latch_lsw = S626_LP_CNTR2ALSW, .my_event_bits = S626_EVBITS(2), }, { .get_enable = s626_get_enable_b, @@ -1269,9 +1292,9 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_b, .set_mode = s626_set_mode_b, .reset_cap_flags = s626_reset_cap_flags_b, - .my_cra = LP_CR0A, - .my_crb = LP_CR0B, - .my_latch_lsw = LP_CNTR0BLSW, + .my_cra = S626_LP_CR0A, + .my_crb = S626_LP_CR0B, + .my_latch_lsw = S626_LP_CNTR0BLSW, .my_event_bits = S626_EVBITS(3), }, { .get_enable = s626_get_enable_b, @@ -1284,9 +1307,9 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_b, .set_mode = s626_set_mode_b, .reset_cap_flags = s626_reset_cap_flags_b, - .my_cra = LP_CR1A, - .my_crb = LP_CR1B, - .my_latch_lsw = LP_CNTR1BLSW, + .my_cra = S626_LP_CR1A, + .my_crb = S626_LP_CR1B, + .my_latch_lsw = S626_LP_CNTR1BLSW, .my_event_bits = S626_EVBITS(4), }, { .get_enable = s626_get_enable_b, @@ -1299,9 +1322,9 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_b, .set_mode = s626_set_mode_b, .reset_cap_flags = s626_reset_cap_flags_b, - .my_cra = LP_CR2A, - .my_crb = LP_CR2B, - .my_latch_lsw = LP_CNTR2BLSW, + .my_cra = S626_LP_CR2A, + .my_crb = S626_LP_CR2B, + .my_latch_lsw = S626_LP_CNTR2BLSW, .my_event_bits = S626_EVBITS(5), }, }; @@ -1326,19 +1349,19 @@ static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan) unsigned int status; /* set channel to capture positive edge */ - status = s626_debi_read(dev, LP_RDEDGSEL(group)); - s626_debi_write(dev, LP_WREDGSEL(group), mask | status); + status = s626_debi_read(dev, S626_LP_RDEDGSEL(group)); + s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status); /* enable interrupt on selected channel */ - status = s626_debi_read(dev, LP_RDINTSEL(group)); - s626_debi_write(dev, LP_WRINTSEL(group), mask | status); + status = s626_debi_read(dev, S626_LP_RDINTSEL(group)); + s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status); /* enable edge capture write command */ - s626_debi_write(dev, LP_MISC1, MISC1_EDCAP); + s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP); /* enable edge capture on selected channel */ - status = s626_debi_read(dev, LP_RDCAPSEL(group)); - s626_debi_write(dev, LP_WRCAPSEL(group), mask | status); + status = s626_debi_read(dev, S626_LP_RDCAPSEL(group)); + s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status); return 0; } @@ -1347,10 +1370,10 @@ static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group, unsigned int mask) { /* disable edge capture write command */ - s626_debi_write(dev, LP_MISC1, MISC1_NOEDCAP); + s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); /* enable edge capture on selected channel */ - s626_debi_write(dev, LP_WRCAPSEL(group), mask); + s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask); return 0; } @@ -1360,11 +1383,11 @@ static int s626_dio_clear_irq(struct comedi_device *dev) unsigned int group; /* disable edge capture write command */ - s626_debi_write(dev, LP_MISC1, MISC1_NOEDCAP); + s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); /* clear all dio pending events and interrupt */ for (group = 0; group < S626_DIO_BANKS; group++) - s626_debi_write(dev, LP_WRCAPSEL(group), 0xffff); + s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff); return 0; } @@ -1383,7 +1406,7 @@ static void s626_handle_dio_interrupt(struct comedi_device *dev, if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 && cmd->start_src == TRIG_EXT) { /* Start executing the RPS program */ - s626_mc_enable(dev, MC1_ERPS1, P_MC1); + s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); if (cmd->scan_begin_src == TRIG_EXT) s626_dio_set_irq(dev, cmd->scan_begin_arg); @@ -1391,7 +1414,7 @@ static void s626_handle_dio_interrupt(struct comedi_device *dev, if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 && cmd->scan_begin_src == TRIG_EXT) { /* Trigger ADC scan loop start */ - s626_mc_enable(dev, MC2_ADC_RPS, P_MC2); + s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); if (cmd->convert_src == TRIG_EXT) { devpriv->ai_convert_count = cmd->chanlist_len; @@ -1404,13 +1427,13 @@ static void s626_handle_dio_interrupt(struct comedi_device *dev, &s626_enc_chan_info[5]; devpriv->ai_convert_count = cmd->chanlist_len; - k->set_enable(dev, k, CLKENAB_ALWAYS); + k->set_enable(dev, k, S626_CLKENAB_ALWAYS); } } if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 && cmd->convert_src == TRIG_EXT) { /* Trigger ADC scan loop start */ - s626_mc_enable(dev, MC2_ADC_RPS, P_MC2); + s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); devpriv->ai_convert_count--; if (devpriv->ai_convert_count > 0) @@ -1427,7 +1450,7 @@ static void s626_check_dio_interrupts(struct comedi_device *dev) for (group = 0; group < S626_DIO_BANKS; group++) { irqbit = 0; /* read interrupt type */ - irqbit = s626_debi_read(dev, LP_RDCAPFLG(group)); + irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group)); /* check if interrupt is generated from dio channels */ if (irqbit) { @@ -1447,34 +1470,34 @@ static void s626_check_counter_interrupts(struct comedi_device *dev) uint16_t irqbit; /* read interrupt type */ - irqbit = s626_debi_read(dev, LP_RDMISC2); + irqbit = s626_debi_read(dev, S626_LP_RDMISC2); /* check interrupt on counters */ - if (irqbit & IRQ_COINT1A) { + if (irqbit & S626_IRQ_COINT1A) { k = &s626_enc_chan_info[0]; /* clear interrupt capture flag */ k->reset_cap_flags(dev, k); } - if (irqbit & IRQ_COINT2A) { + if (irqbit & S626_IRQ_COINT2A) { k = &s626_enc_chan_info[1]; /* clear interrupt capture flag */ k->reset_cap_flags(dev, k); } - if (irqbit & IRQ_COINT3A) { + if (irqbit & S626_IRQ_COINT3A) { k = &s626_enc_chan_info[2]; /* clear interrupt capture flag */ k->reset_cap_flags(dev, k); } - if (irqbit & IRQ_COINT1B) { + if (irqbit & S626_IRQ_COINT1B) { k = &s626_enc_chan_info[3]; /* clear interrupt capture flag */ k->reset_cap_flags(dev, k); } - if (irqbit & IRQ_COINT2B) { + if (irqbit & S626_IRQ_COINT2B) { k = &s626_enc_chan_info[4]; /* clear interrupt capture flag */ @@ -1483,15 +1506,16 @@ static void s626_check_counter_interrupts(struct comedi_device *dev) if (devpriv->ai_convert_count > 0) { devpriv->ai_convert_count--; if (devpriv->ai_convert_count == 0) - k->set_enable(dev, k, CLKENAB_INDEX); + k->set_enable(dev, k, S626_CLKENAB_INDEX); if (cmd->convert_src == TRIG_TIMER) { /* Trigger ADC scan loop start */ - s626_mc_enable(dev, MC2_ADC_RPS, P_MC2); + s626_mc_enable(dev, S626_MC2_ADC_RPS, + S626_P_MC2); } } } - if (irqbit & IRQ_COINT3B) { + if (irqbit & S626_IRQ_COINT3B) { k = &s626_enc_chan_info[5]; /* clear interrupt capture flag */ @@ -1499,13 +1523,13 @@ static void s626_check_counter_interrupts(struct comedi_device *dev) if (cmd->scan_begin_src == TRIG_TIMER) { /* Trigger ADC scan loop start */ - s626_mc_enable(dev, MC2_ADC_RPS, P_MC2); + s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); } if (cmd->convert_src == TRIG_TIMER) { k = &s626_enc_chan_info[4]; devpriv->ai_convert_count = cmd->chanlist_len; - k->set_enable(dev, k, CLKENAB_ALWAYS); + k->set_enable(dev, k, S626_CLKENAB_ALWAYS); } } } @@ -1550,7 +1574,7 @@ static bool s626_handle_eos_interrupt(struct comedi_device *dev) devpriv->ai_cmd_running = 0; /* Stop RPS program */ - s626_mc_disable(dev, MC1_ERPS1, P_MC1); + s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); /* send end of acquisition */ async->events |= COMEDI_CB_EOA; @@ -1581,23 +1605,23 @@ static irqreturn_t s626_irq_handler(int irq, void *d) spin_lock_irqsave(&dev->spinlock, flags); /* save interrupt enable register state */ - irqstatus = readl(devpriv->mmio + P_IER); + irqstatus = readl(devpriv->mmio + S626_P_IER); /* read interrupt type */ - irqtype = readl(devpriv->mmio + P_ISR); + irqtype = readl(devpriv->mmio + S626_P_ISR); /* disable master interrupt */ - writel(0, devpriv->mmio + P_IER); + writel(0, devpriv->mmio + S626_P_IER); /* clear interrupt */ - writel(irqtype, devpriv->mmio + P_ISR); + writel(irqtype, devpriv->mmio + S626_P_ISR); switch (irqtype) { - case IRQ_RPS1: /* end_of_scan occurs */ + case S626_IRQ_RPS1: /* end_of_scan occurs */ if (s626_handle_eos_interrupt(dev)) irqstatus = 0; break; - case IRQ_GPIO3: /* check dio and counter interrupt */ + case S626_IRQ_GPIO3: /* check dio and counter interrupt */ /* s626_dio_clear_irq(dev); */ s626_check_dio_interrupts(dev); s626_check_counter_interrupts(dev); @@ -1605,7 +1629,7 @@ static irqreturn_t s626_irq_handler(int irq, void *d) } /* enable interrupt */ - writel(irqstatus, devpriv->mmio + P_IER); + writel(irqstatus, devpriv->mmio + S626_P_IER); spin_unlock_irqrestore(&dev->spinlock, flags); return IRQ_HANDLED; @@ -1625,20 +1649,20 @@ static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl) struct comedi_cmd *cmd = &dev->subdevices->async->cmd; /* Stop RPS program in case it is currently running */ - s626_mc_disable(dev, MC1_ERPS1, P_MC1); + s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); /* Set starting logical address to write RPS commands. */ rps = (uint32_t *)devpriv->rps_buf.logical_base; /* Initialize RPS instruction pointer */ writel((uint32_t)devpriv->rps_buf.physical_base, - devpriv->mmio + P_RPSADDR1); + devpriv->mmio + S626_P_RPSADDR1); /* Construct RPS program in rps_buf DMA buffer */ if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) { /* Wait for Start trigger. */ - *rps++ = RPS_PAUSE | RPS_SIGADC; - *rps++ = RPS_CLRSIGNAL | RPS_SIGADC; + *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; + *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; } /* @@ -1650,20 +1674,22 @@ static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl) * the previously programmed value. */ /* Write DEBI Write command and address to shadow RAM. */ - *rps++ = RPS_LDREG | (P_DEBICMD >> 2); - *rps++ = DEBI_CMD_WRWORD | LP_GSEL; - *rps++ = RPS_LDREG | (P_DEBIAD >> 2); + *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); + *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; + *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); /* Write DEBI immediate data to shadow RAM: */ - *rps++ = GSEL_BIPOLAR5V; /* arbitrary immediate data value. */ - *rps++ = RPS_CLRSIGNAL | RPS_DEBI; + *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */ + *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; /* Reset "shadow RAM uploaded" flag. */ - *rps++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */ - *rps++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */ + /* Invoke shadow RAM upload. */ + *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; + /* Wait for shadow upload to finish. */ + *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; /* * Digitize all slots in the poll list. This is implemented as a * for loop to limit the slot count to 16 in case the application - * forgot to set the EOPL flag in the final slot. + * forgot to set the S626_EOPL flag in the final slot. */ for (devpriv->adc_items = 0; devpriv->adc_items < 16; devpriv->adc_items++) { @@ -1673,77 +1699,80 @@ static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl) * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 = * +-10V, 1 = +-5V, and EOPL = End of Poll List marker. */ - local_ppl = (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V : - GSEL_BIPOLAR10V); + local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V : + S626_GSEL_BIPOLAR10V); /* Switch ADC analog gain. */ /* Write DEBI command and address to shadow RAM. */ - *rps++ = RPS_LDREG | (P_DEBICMD >> 2); - *rps++ = DEBI_CMD_WRWORD | LP_GSEL; + *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); + *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; /* Write DEBI immediate data to shadow RAM. */ - *rps++ = RPS_LDREG | (P_DEBIAD >> 2); + *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); *rps++ = local_ppl; /* Reset "shadow RAM uploaded" flag. */ - *rps++ = RPS_CLRSIGNAL | RPS_DEBI; + *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; /* Invoke shadow RAM upload. */ - *rps++ = RPS_UPLOAD | RPS_DEBI; + *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; /* Wait for shadow upload to finish. */ - *rps++ = RPS_PAUSE | RPS_DEBI; + *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; /* Select ADC analog input channel. */ - *rps++ = RPS_LDREG | (P_DEBICMD >> 2); + *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); /* Write DEBI command and address to shadow RAM. */ - *rps++ = DEBI_CMD_WRWORD | LP_ISEL; - *rps++ = RPS_LDREG | (P_DEBIAD >> 2); + *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL; + *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); /* Write DEBI immediate data to shadow RAM. */ *rps++ = local_ppl; /* Reset "shadow RAM uploaded" flag. */ - *rps++ = RPS_CLRSIGNAL | RPS_DEBI; + *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; /* Invoke shadow RAM upload. */ - *rps++ = RPS_UPLOAD | RPS_DEBI; + *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; /* Wait for shadow upload to finish. */ - *rps++ = RPS_PAUSE | RPS_DEBI; + *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; /* * Delay at least 10 microseconds for analog input settling. - * Instead of padding with NOPs, we use RPS_JUMP instructions - * here; this allows us to produce a longer delay than is - * possible with NOPs because each RPS_JUMP flushes the RPS' - * instruction prefetch pipeline. + * Instead of padding with NOPs, we use S626_RPS_JUMP + * instructions here; this allows us to produce a longer delay + * than is possible with NOPs because each S626_RPS_JUMP + * flushes the RPS' instruction prefetch pipeline. */ jmp_adrs = (uint32_t)devpriv->rps_buf.physical_base + (uint32_t)((unsigned long)rps - (unsigned long)devpriv-> rps_buf.logical_base); - for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) { + for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) { jmp_adrs += 8; /* Repeat to implement time delay: */ - *rps++ = RPS_JUMP; /* Jump to next RPS instruction. */ + /* Jump to next RPS instruction. */ + *rps++ = S626_RPS_JUMP; *rps++ = jmp_adrs; } if (cmd != NULL && cmd->convert_src != TRIG_NOW) { /* Wait for Start trigger. */ - *rps++ = RPS_PAUSE | RPS_SIGADC; - *rps++ = RPS_CLRSIGNAL | RPS_SIGADC; + *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; + *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; } /* Start ADC by pulsing GPIO1. */ /* Begin ADC Start pulse. */ - *rps++ = RPS_LDREG | (P_GPIO >> 2); - *rps++ = GPIO_BASE | GPIO1_LO; - *rps++ = RPS_NOP; + *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); + *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; + *rps++ = S626_RPS_NOP; /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ /* End ADC Start pulse. */ - *rps++ = RPS_LDREG | (P_GPIO >> 2); - *rps++ = GPIO_BASE | GPIO1_HI; + *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); + *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; /* * Wait for ADC to complete (GPIO2 is asserted high when ADC not * busy) and for data from previous conversion to shift into FB * BUFFER 1 register. */ - *rps++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */ + /* Wait for ADC done. */ + *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */ - *rps++ = RPS_STREG | (S626_BUGFIX_STREG(P_FB_BUFFER1) >> 2); + *rps++ = S626_RPS_STREG | + (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); *rps++ = (uint32_t)devpriv->ana_buf.physical_base + (devpriv->adc_items << 2); @@ -1751,7 +1780,7 @@ static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl) * If this slot's EndOfPollList flag is set, all channels have * now been processed. */ - if (*ppl++ & EOPL) { + if (*ppl++ & S626_EOPL) { devpriv->adc_items++; /* Adjust poll list item count. */ break; /* Exit poll list processing loop. */ } @@ -1765,41 +1794,42 @@ static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl) * conversion. Without this delay, the last conversion's data value * is sometimes set to the previous conversion's data value. */ - for (n = 0; n < (2 * RPSCLK_PER_US); n++) - *rps++ = RPS_NOP; + for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++) + *rps++ = S626_RPS_NOP; /* * Start a dummy conversion to cause the data from the last * conversion of interest to be shifted in. */ - *rps++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */ - *rps++ = GPIO_BASE | GPIO1_LO; - *rps++ = RPS_NOP; + /* Begin ADC Start pulse. */ + *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); + *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; + *rps++ = S626_RPS_NOP; /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ - *rps++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */ - *rps++ = GPIO_BASE | GPIO1_HI; + *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */ + *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; /* * Wait for the data from the last conversion of interest to arrive * in FB BUFFER 1 register. */ - *rps++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */ + *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Wait for ADC done. */ /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */ - *rps++ = RPS_STREG | (S626_BUGFIX_STREG(P_FB_BUFFER1) >> 2); + *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); *rps++ = (uint32_t)devpriv->ana_buf.physical_base + (devpriv->adc_items << 2); /* Indicate ADC scan loop is finished. */ /* Signal ReadADC() that scan is done. */ - /* *rps++= RPS_CLRSIGNAL | RPS_SIGADC; */ + /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */ /* invoke interrupt */ if (devpriv->ai_cmd_running == 1) - *rps++ = RPS_IRQ; + *rps++ = S626_RPS_IRQ; /* Restart RPS program at its beginning. */ - *rps++ = RPS_JUMP; /* Branch to start of RPS program. */ + *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */ *rps++ = (uint32_t)devpriv->rps_buf.physical_base; /* End of RPS program build */ @@ -1816,10 +1846,10 @@ static int s626_ai_rinsn(struct comedi_device *dev, int32_t *readaddr; /* Trigger ADC scan loop start */ - s626_mc_enable(dev, MC2_ADC_RPS, P_MC2); + s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */ - while (s626_mc_test(dev, MC2_ADC_RPS, P_MC2)) + while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2)) ; /* @@ -1859,29 +1889,32 @@ static int s626_ai_insn_read(struct comedi_device *dev, * appropriate for register programming. */ if (range == 0) - adc_spec = (chan << 8) | (GSEL_BIPOLAR5V); + adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V); else - adc_spec = (chan << 8) | (GSEL_BIPOLAR10V); + adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V); /* Switch ADC analog gain. */ - s626_debi_write(dev, LP_GSEL, adc_spec); /* Set gain. */ + s626_debi_write(dev, S626_LP_GSEL, adc_spec); /* Set gain. */ /* Select ADC analog input channel. */ - s626_debi_write(dev, LP_ISEL, adc_spec); /* Select channel. */ + s626_debi_write(dev, S626_LP_ISEL, adc_spec); /* Select channel. */ for (n = 0; n < insn->n; n++) { /* Delay 10 microseconds for analog input settling. */ udelay(10); /* Start ADC by pulsing GPIO1 low */ - gpio_image = readl(devpriv->mmio + P_GPIO); + gpio_image = readl(devpriv->mmio + S626_P_GPIO); /* Assert ADC Start command */ - writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO); + writel(gpio_image & ~S626_GPIO1_HI, + devpriv->mmio + S626_P_GPIO); /* and stretch it out */ - writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO); - writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO); + writel(gpio_image & ~S626_GPIO1_HI, + devpriv->mmio + S626_P_GPIO); + writel(gpio_image & ~S626_GPIO1_HI, + devpriv->mmio + S626_P_GPIO); /* Negate ADC Start command */ - writel(gpio_image | GPIO1_HI, devpriv->mmio + P_GPIO); + writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); /* * Wait for ADC to complete (GPIO2 is asserted high when @@ -1890,12 +1923,12 @@ static int s626_ai_insn_read(struct comedi_device *dev, */ /* Wait for ADC done */ - while (!(readl(devpriv->mmio + P_PSR) & PSR_GPIO2)) + while (!(readl(devpriv->mmio + S626_P_PSR) & S626_PSR_GPIO2)) ; /* Fetch ADC data */ if (n != 0) { - tmp = readl(devpriv->mmio + P_FB_BUFFER1); + tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1); data[n - 1] = s626_ai_reg_to_uint(tmp); } @@ -1915,26 +1948,26 @@ static int s626_ai_insn_read(struct comedi_device *dev, * Start a dummy conversion to cause the data from the * previous conversion to be shifted in. */ - gpio_image = readl(devpriv->mmio + P_GPIO); + gpio_image = readl(devpriv->mmio + S626_P_GPIO); /* Assert ADC Start command */ - writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO); + writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); /* and stretch it out */ - writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO); - writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO); + writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); + writel(gpio_image & ~S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); /* Negate ADC Start command */ - writel(gpio_image | GPIO1_HI, devpriv->mmio + P_GPIO); + writel(gpio_image | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); /* Wait for the data to arrive in FB BUFFER 1 register. */ /* Wait for ADC done */ - while (!(readl(devpriv->mmio + P_PSR) & PSR_GPIO2)) + while (!(readl(devpriv->mmio + S626_P_PSR) & S626_PSR_GPIO2)) ; /* Fetch ADC data from audio interface's input shift register. */ /* Fetch ADC data */ if (n != 0) { - tmp = readl(devpriv->mmio + P_FB_BUFFER1); + tmp = readl(devpriv->mmio + S626_P_FB_BUFFER1); data[n - 1] = s626_ai_reg_to_uint(tmp); } @@ -1947,12 +1980,12 @@ static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd) for (n = 0; n < cmd->chanlist_len; n++) { if (CR_RANGE(cmd->chanlist[n]) == 0) - ppl[n] = CR_CHAN(cmd->chanlist[n]) | RANGE_5V; + ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V; else - ppl[n] = CR_CHAN(cmd->chanlist[n]) | RANGE_10V; + ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V; } if (n != 0) - ppl[n - 1] |= EOPL; + ppl[n - 1] |= S626_EOPL; return n; } @@ -1964,7 +1997,7 @@ static int s626_ai_inttrig(struct comedi_device *dev, return -EINVAL; /* Start executing the RPS program */ - s626_mc_enable(dev, MC1_ERPS1, P_MC1); + s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); s->async->inttrig = NULL; @@ -2005,15 +2038,21 @@ static void s626_timer_load(struct comedi_device *dev, const struct s626_enc_info *k, int tick) { uint16_t setup = - (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon index. */ - (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */ - (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */ - (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */ - (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */ - (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */ - (CLKENAB_INDEX << BF_CLKENAB); - uint16_t value_latchsrc = LATCHSRC_A_INDXA; - /* uint16_t enab = CLKENAB_ALWAYS; */ + /* Preload upon index. */ + (S626_LOADSRC_INDX << S626_BF_LOADSRC) | + /* Disable hardware index. */ + (S626_INDXSRC_SOFT << S626_BF_INDXSRC) | + /* Operating mode is Timer. */ + (S626_CLKSRC_TIMER << S626_BF_CLKSRC) | + /* Active high clock. */ + (S626_CLKPOL_POS << S626_BF_CLKPOL) | + /* Count direction is Down. */ + (S626_CNTDIR_DOWN << S626_BF_CLKPOL) | + /* Clock multiplier is 1x. */ + (S626_CLKMULT_1X << S626_BF_CLKMULT) | + (S626_CLKENAB_INDEX << S626_BF_CLKENAB); + uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA; + /* uint16_t enab = S626_CLKENAB_ALWAYS; */ k->set_mode(dev, k, setup, false); @@ -2031,7 +2070,7 @@ static void s626_timer_load(struct comedi_device *dev, k->set_load_trig(dev, k, 1); /* set interrupt on overflow */ - k->set_int_src(dev, k, INTSRC_OVER); + k->set_int_src(dev, k, S626_INTSRC_OVER); s626_set_latch_source(dev, k, value_latchsrc); /* k->set_enable(dev, k, (uint16_t)(enab != 0)); */ @@ -2052,10 +2091,10 @@ static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) return -EBUSY; } /* disable interrupt */ - writel(0, devpriv->mmio + P_IER); + writel(0, devpriv->mmio + S626_P_IER); /* clear interrupt request */ - writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->mmio + P_ISR); + writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, devpriv->mmio + S626_P_ISR); /* clear any pending interrupt */ s626_dio_clear_irq(dev); @@ -2092,7 +2131,7 @@ static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* load timer value and enable interrupt */ s626_timer_load(dev, k, tick); - k->set_enable(dev, k, CLKENAB_ALWAYS); + k->set_enable(dev, k, S626_CLKENAB_ALWAYS); break; case TRIG_EXT: /* set the digital line and interrupt for scan trigger */ @@ -2115,7 +2154,7 @@ static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* load timer value and enable interrupt */ s626_timer_load(dev, k, tick); - k->set_enable(dev, k, CLKENAB_INDEX); + k->set_enable(dev, k, S626_CLKENAB_INDEX); break; case TRIG_EXT: /* set the digital line and interrupt for convert trigger */ @@ -2143,10 +2182,10 @@ static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) switch (cmd->start_src) { case TRIG_NOW: /* Trigger ADC scan loop start */ - /* s626_mc_enable(dev, MC2_ADC_RPS, P_MC2); */ + /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */ /* Start executing the RPS program */ - s626_mc_enable(dev, MC1_ERPS1, P_MC1); + s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); s->async->inttrig = NULL; break; case TRIG_EXT: @@ -2160,7 +2199,7 @@ static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) } /* enable interrupt */ - writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->mmio + P_IER); + writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, devpriv->mmio + S626_P_IER); return 0; } @@ -2278,10 +2317,10 @@ static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) struct s626_private *devpriv = dev->private; /* Stop RPS program in case it is currently running */ - s626_mc_disable(dev, MC1_ERPS1, P_MC1); + s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); /* disable master interrupt */ - writel(0, devpriv->mmio + P_IER); + writel(0, devpriv->mmio + S626_P_IER); devpriv->ai_cmd_running = 0; @@ -2332,18 +2371,18 @@ static void s626_dio_init(struct comedi_device *dev) uint16_t group; /* Prepare to treat writes to WRCapSel as capture disables. */ - s626_debi_write(dev, LP_MISC1, MISC1_NOEDCAP); + s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); /* For each group of sixteen channels ... */ for (group = 0; group < S626_DIO_BANKS; group++) { /* Disable all interrupts */ - s626_debi_write(dev, LP_WRINTSEL(group), 0); + s626_debi_write(dev, S626_LP_WRINTSEL(group), 0); /* Disable all event captures */ - s626_debi_write(dev, LP_WRCAPSEL(group), 0xffff); + s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff); /* Init all DIOs to default edge polarity */ - s626_debi_write(dev, LP_WREDGSEL(group), 0); + s626_debi_write(dev, S626_LP_WREDGSEL(group), 0); /* Program all outputs to inactive state */ - s626_debi_write(dev, LP_WRDOUT(group), 0); + s626_debi_write(dev, S626_LP_WRDOUT(group), 0); } } @@ -2355,9 +2394,9 @@ static int s626_dio_insn_bits(struct comedi_device *dev, unsigned long group = (unsigned long)s->private; if (comedi_dio_update_state(s, data)) - s626_debi_write(dev, LP_WRDOUT(group), s->state); + s626_debi_write(dev, S626_LP_WRDOUT(group), s->state); - data[1] = s626_debi_read(dev, LP_RDDIN(group)); + data[1] = s626_debi_read(dev, S626_LP_RDDIN(group)); return insn->n; } @@ -2374,7 +2413,7 @@ static int s626_dio_insn_config(struct comedi_device *dev, if (ret) return ret; - s626_debi_write(dev, LP_WRDOUT(group), s->io_bits); + s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits); return insn->n; } @@ -2393,16 +2432,21 @@ static int s626_enc_insn_config(struct comedi_device *dev, struct comedi_insn *insn, unsigned int *data) { uint16_t setup = - (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon index. */ - (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */ - (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */ - (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */ - (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */ - (CLKENAB_INDEX << BF_CLKENAB); + /* Preload upon index. */ + (S626_LOADSRC_INDX << S626_BF_LOADSRC) | + /* Disable hardware index. */ + (S626_INDXSRC_SOFT << S626_BF_INDXSRC) | + /* Operating mode is Counter. */ + (S626_CLKSRC_COUNTER << S626_BF_CLKSRC) | + /* Active high clock. */ + (S626_CLKPOL_POS << S626_BF_CLKPOL) | + /* Clock multiplier is 1x. */ + (S626_CLKMULT_1X << S626_BF_CLKMULT) | + (S626_CLKENAB_INDEX << S626_BF_CLKENAB); /* uint16_t disable_int_src = true; */ /* uint32_t Preloadvalue; //Counter initial value */ - uint16_t value_latchsrc = LATCHSRC_AB_READ; - uint16_t enab = CLKENAB_ALWAYS; + uint16_t value_latchsrc = S626_LATCHSRC_AB_READ; + uint16_t enab = S626_CLKENAB_ALWAYS; const struct s626_enc_info *k = &s626_enc_chan_info[CR_CHAN(insn->chanspec)]; @@ -2454,9 +2498,9 @@ static int s626_enc_insn_write(struct comedi_device *dev, static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image) { - s626_debi_write(dev, LP_MISC1, MISC1_WENABLE); - s626_debi_write(dev, LP_WRMISC2, new_image); - s626_debi_write(dev, LP_MISC1, MISC1_WDISABLE); + s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE); + s626_debi_write(dev, S626_LP_WRMISC2, new_image); + s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE); } static void s626_close_dma_b(struct comedi_device *dev, @@ -2484,13 +2528,20 @@ static void s626_counters_init(struct comedi_device *dev) int chan; const struct s626_enc_info *k; uint16_t setup = - (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon index. */ - (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */ - (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */ - (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */ - (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */ - (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */ - (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */ + /* Preload upon index. */ + (S626_LOADSRC_INDX << S626_BF_LOADSRC) | + /* Disable hardware index. */ + (S626_INDXSRC_SOFT << S626_BF_INDXSRC) | + /* Operating mode is counter. */ + (S626_CLKSRC_COUNTER << S626_BF_CLKSRC) | + /* Active high clock. */ + (S626_CLKPOL_POS << S626_BF_CLKPOL) | + /* Count direction is up. */ + (S626_CNTDIR_UP << S626_BF_CLKPOL) | + /* Clock multiplier is 1x. */ + (S626_CLKMULT_1X << S626_BF_CLKMULT) | + /* Enabled by index */ + (S626_CLKENAB_INDEX << S626_BF_CLKENAB); /* * Disable all counter interrupts and clear any captured counter events. @@ -2500,7 +2551,7 @@ static void s626_counters_init(struct comedi_device *dev) k->set_mode(dev, k, setup, true); k->set_int_src(dev, k, 0); k->reset_cap_flags(dev, k); - k->set_enable(dev, k, CLKENAB_ALWAYS); + k->set_enable(dev, k, S626_CLKENAB_ALWAYS); } } @@ -2511,13 +2562,13 @@ static int s626_allocate_dma_buffers(struct comedi_device *dev) void *addr; dma_addr_t appdma; - addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma); + addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma); if (!addr) return -ENOMEM; devpriv->ana_buf.logical_base = addr; devpriv->ana_buf.physical_base = appdma; - addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma); + addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma); if (!addr) return -ENOMEM; devpriv->rps_buf.logical_base = addr; @@ -2534,7 +2585,8 @@ static void s626_initialize(struct comedi_device *dev) int i; /* Enable DEBI and audio pins, enable I2C interface */ - s626_mc_enable(dev, MC1_DEBI | MC1_AUDIO | MC1_I2C, P_MC1); + s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C, + S626_P_MC1); /* * Configure DEBI operating mode @@ -2544,14 +2596,15 @@ static void s626_initialize(struct comedi_device *dev) * Set up byte lane steering * Intel-compatible local bus (DEBI never times out) */ - writel(DEBI_CFG_SLAVE16 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) | - DEBI_SWAP | DEBI_CFG_INTEL, devpriv->mmio + P_DEBICFG); + writel(S626_DEBI_CFG_SLAVE16 | + (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP | + S626_DEBI_CFG_INTEL, devpriv->mmio + S626_P_DEBICFG); /* Disable MMU paging */ - writel(DEBI_PAGE_DISABLE, devpriv->mmio + P_DEBIPAGE); + writel(S626_DEBI_PAGE_DISABLE, devpriv->mmio + S626_P_DEBIPAGE); /* Init GPIO so that ADC Start* is negated */ - writel(GPIO_BASE | GPIO1_HI, devpriv->mmio + P_GPIO); + writel(S626_GPIO_BASE | S626_GPIO1_HI, devpriv->mmio + S626_P_GPIO); /* I2C device address for onboard eeprom (revb) */ devpriv->i2c_adrs = 0xA0; @@ -2560,9 +2613,10 @@ static void s626_initialize(struct comedi_device *dev) * Issue an I2C ABORT command to halt any I2C * operation in progress and reset BUSY flag. */ - writel(I2C_CLKSEL | I2C_ABORT, devpriv->mmio + P_I2CSTAT); - s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2); - while (!(readl(devpriv->mmio + P_MC2) & MC2_UPLD_IIC)) + writel(S626_I2C_CLKSEL | S626_I2C_ABORT, + devpriv->mmio + S626_P_I2CSTAT); + s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); + while (!(readl(devpriv->mmio + S626_P_MC2) & S626_MC2_UPLD_IIC)) ; /* @@ -2570,9 +2624,9 @@ static void s626_initialize(struct comedi_device *dev) * reg twice to reset all I2C error flags. */ for (i = 0; i < 2; i++) { - writel(I2C_CLKSEL, devpriv->mmio + P_I2CSTAT); - s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2); - while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2)) + writel(S626_I2C_CLKSEL, devpriv->mmio + S626_P_I2CSTAT); + s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); + while (!s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2)) ; } @@ -2582,19 +2636,20 @@ static void s626_initialize(struct comedi_device *dev) * DAC data setup times are satisfied, enable DAC serial * clock out. */ - writel(ACON2_INIT, devpriv->mmio + P_ACON2); + writel(S626_ACON2_INIT, devpriv->mmio + S626_P_ACON2); /* * Set up TSL1 slot list, which is used to control the - * accumulation of ADC data: RSD1 = shift data in on SD1. - * SIB_A1 = store data uint8_t at next available location + * accumulation of ADC data: S626_RSD1 = shift data in on SD1. + * S626_SIB_A1 = store data uint8_t at next available location * in FB BUFFER1 register. */ - writel(RSD1 | SIB_A1, devpriv->mmio + P_TSL1); - writel(RSD1 | SIB_A1 | EOS, devpriv->mmio + P_TSL1 + 4); + writel(S626_RSD1 | S626_SIB_A1, devpriv->mmio + S626_P_TSL1); + writel(S626_RSD1 | S626_SIB_A1 | S626_EOS, + devpriv->mmio + S626_P_TSL1 + 4); /* Enable TSL1 slot list so that it executes all the time */ - writel(ACON1_ADCSTART, devpriv->mmio + P_ACON1); + writel(S626_ACON1_ADCSTART, devpriv->mmio + S626_P_ACON1); /* * Initialize RPS registers used for ADC @@ -2602,11 +2657,11 @@ static void s626_initialize(struct comedi_device *dev) /* Physical start of RPS program */ writel((uint32_t)devpriv->rps_buf.physical_base, - devpriv->mmio + P_RPSADDR1); + devpriv->mmio + S626_P_RPSADDR1); /* RPS program performs no explicit mem writes */ - writel(0, devpriv->mmio + P_RPSPAGE1); + writel(0, devpriv->mmio + S626_P_RPSPAGE1); /* Disable RPS timeouts */ - writel(0, devpriv->mmio + P_RPS1_TOUT); + writel(0, devpriv->mmio + S626_P_RPS1_TOUT); #if 0 /* @@ -2626,7 +2681,7 @@ static void s626_initialize(struct comedi_device *dev) unsigned int data[16]; /* Create a simple polling list for analog input channel 0 */ - poll_list = EOPL; + poll_list = S626_EOPL; s626_reset_adc(dev, &poll_list); /* Get initial ADC value */ @@ -2661,7 +2716,7 @@ static void s626_initialize(struct comedi_device *dev) * burst length = 1 DWORD * threshold = 1 DWORD. */ - writel(0, devpriv->mmio + P_PCI_BT_A); + writel(0, devpriv->mmio + S626_P_PCI_BT_A); /* * Init Audio2's output DMA physical addresses. The protection @@ -2670,17 +2725,17 @@ static void s626_initialize(struct comedi_device *dev) * enabled. */ phys_buf = devpriv->ana_buf.physical_base + - (DAC_WDMABUF_OS * sizeof(uint32_t)); - writel((uint32_t)phys_buf, devpriv->mmio + P_BASEA2_OUT); + (S626_DAC_WDMABUF_OS * sizeof(uint32_t)); + writel((uint32_t)phys_buf, devpriv->mmio + S626_P_BASEA2_OUT); writel((uint32_t)(phys_buf + sizeof(uint32_t)), - devpriv->mmio + P_PROTA2_OUT); + devpriv->mmio + S626_P_PROTA2_OUT); /* * Cache Audio2's output DMA buffer logical address. This is * where DAC data is buffered for A2 output DMA transfers. */ devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base + - DAC_WDMABUF_OS; + S626_DAC_WDMABUF_OS; /* * Audio2's output channels does not use paging. The @@ -2688,7 +2743,7 @@ static void s626_initialize(struct comedi_device *dev) * DMAC will automatically halt and its PCI address pointer * will be reset when the protection address is reached. */ - writel(8, devpriv->mmio + P_PAGEA2_OUT); + writel(8, devpriv->mmio + S626_P_PAGEA2_OUT); /* * Initialize time slot list 2 (TSL2), which is used to control @@ -2703,7 +2758,8 @@ static void s626_initialize(struct comedi_device *dev) */ /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */ - writel(XSD2 | RSD3 | SIB_A2 | EOS, devpriv->mmio + S626_VECTPORT(0)); + writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS, + devpriv->mmio + S626_VECTPORT(0)); /* * Initialize slot 1, which is constant. Slot 1 causes a @@ -2715,10 +2771,10 @@ static void s626_initialize(struct comedi_device *dev) */ /* Slot 1: Fetch DWORD from Audio2's output FIFO */ - writel(LF_A2, devpriv->mmio + S626_VECTPORT(1)); + writel(S626_LF_A2, devpriv->mmio + S626_VECTPORT(1)); /* Start DAC's audio interface (TSL2) running */ - writel(ACON1_DACSTART, devpriv->mmio + P_ACON1); + writel(S626_ACON1_DACSTART, devpriv->mmio + S626_P_ACON1); /* * Init Trim DACs to calibrated values. Do it twice because the @@ -2752,8 +2808,8 @@ static void s626_initialize(struct comedi_device *dev) * standard DIO (vs. counter overflow) mode, disable the battery * charger, and reset the watchdog interval selector to zero. */ - s626_write_misc2(dev, (s626_debi_read(dev, LP_RDMISC2) & - MISC2_BATT_ENABLE)); + s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) & + S626_MISC2_BATT_ENABLE)); /* Initialize the digital I/O subsystem */ s626_dio_init(dev); @@ -2780,10 +2836,10 @@ static int s626_auto_attach(struct comedi_device *dev, return -ENOMEM; /* disable master interrupt */ - writel(0, devpriv->mmio + P_IER); + writel(0, devpriv->mmio + S626_P_IER); /* soft reset */ - writel(MC1_SOFT_RESET, devpriv->mmio + P_MC1); + writel(S626_MC1_SOFT_RESET, devpriv->mmio + S626_P_MC1); /* DMA FIXME DMA// */ @@ -2894,20 +2950,22 @@ static void s626_detach(struct comedi_device *dev) if (devpriv->mmio) { /* interrupt mask */ /* Disable master interrupt */ - writel(0, devpriv->mmio + P_IER); + writel(0, devpriv->mmio + S626_P_IER); /* Clear board's IRQ status flag */ - writel(IRQ_GPIO3 | IRQ_RPS1, - devpriv->mmio + P_ISR); + writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, + devpriv->mmio + S626_P_ISR); /* Disable the watchdog timer and battery charger. */ s626_write_misc2(dev, 0); /* Close all interfaces on 7146 device */ - writel(MC1_SHUTDOWN, devpriv->mmio + P_MC1); - writel(ACON1_BASE, devpriv->mmio + P_ACON1); + writel(S626_MC1_SHUTDOWN, devpriv->mmio + S626_P_MC1); + writel(S626_ACON1_BASE, devpriv->mmio + S626_P_ACON1); - s626_close_dma_b(dev, &devpriv->rps_buf, DMABUF_SIZE); - s626_close_dma_b(dev, &devpriv->ana_buf, DMABUF_SIZE); + s626_close_dma_b(dev, &devpriv->rps_buf, + S626_DMABUF_SIZE); + s626_close_dma_b(dev, &devpriv->ana_buf, + S626_DMABUF_SIZE); } if (dev->irq) diff --git a/drivers/staging/comedi/drivers/s626.h b/drivers/staging/comedi/drivers/s626.h index 605926ed861b..9b6ab0d398d6 100644 --- a/drivers/staging/comedi/drivers/s626.h +++ b/drivers/staging/comedi/drivers/s626.h @@ -22,8 +22,7 @@ #ifndef S626_H_INCLUDED #define S626_H_INCLUDED -#define S626_SIZE 0x200 -#define DMABUF_SIZE 4096 /* 4k pages */ +#define S626_DMABUF_SIZE 4096 /* 4k pages */ #define S626_ADC_CHANNELS 16 #define S626_DAC_CHANNELS 4 @@ -33,585 +32,575 @@ #define S626_DIO_EXTCHANS 40 /* Number of extended-capability * DIO channels. */ -#define NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */ +#define S626_NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */ /* PCI bus interface types. */ -#define INTEL 1 /* Intel bus type. */ -#define MOTOROLA 2 /* Motorola bus type. */ +#define S626_INTEL 1 /* Intel bus type. */ +#define S626_MOTOROLA 2 /* Motorola bus type. */ -#define PLATFORM INTEL /* *** SELECT PLATFORM TYPE *** */ +#define S626_PLATFORM S626_INTEL /* *** SELECT PLATFORM TYPE *** */ -#define RANGE_5V 0x10 /* +/-5V range */ -#define RANGE_10V 0x00 /* +/-10V range */ +#define S626_RANGE_5V 0x10 /* +/-5V range */ +#define S626_RANGE_10V 0x00 /* +/-10V range */ -#define EOPL 0x80 /* End of ADC poll list marker. */ -#define GSEL_BIPOLAR5V 0x00F0 /* LP_GSEL setting for 5V bipolar. */ -#define GSEL_BIPOLAR10V 0x00A0 /* LP_GSEL setting for 10V bipolar. */ +#define S626_EOPL 0x80 /* End of ADC poll list marker. */ +#define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */ +#define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */ /* Error codes that must be visible to this base class. */ -#define ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter +#define S626_ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter * value was specified. */ -#define ERR_I2C 0x00020000 /* I2C error. */ -#define ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for +#define S626_ERR_I2C 0x00020000 /* I2C error. */ +#define S626_ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for * counter channel. */ -#define ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */ +#define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */ /* * Organization (physical order) and size (in DWORDs) of logical DMA buffers * contained by ANA_DMABUF. */ -#define ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, +#define S626_ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, * plus pre/post garbage samples. */ -#define DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single +#define S626_DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single * sample. */ /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */ /* Address offsets, in DWORDS, from base of DMA buffer. */ -#define DAC_WDMABUF_OS ADC_DMABUF_DWORDS +#define S626_DAC_WDMABUF_OS S626_ADC_DMABUF_DWORDS /* Interrupt enable bit in ISR and IER. */ -#define IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */ -#define IRQ_RPS1 0x10000000 -#define ISR_AFOU 0x00000800 +#define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */ +#define S626_IRQ_RPS1 0x10000000 +#define S626_ISR_AFOU 0x00000800 /* Audio fifo under/overflow detected. */ -#define IRQ_COINT1A 0x0400 /* counter 1A overflow interrupt mask */ -#define IRQ_COINT1B 0x0800 /* counter 1B overflow interrupt mask */ -#define IRQ_COINT2A 0x1000 /* counter 2A overflow interrupt mask */ -#define IRQ_COINT2B 0x2000 /* counter 2B overflow interrupt mask */ -#define IRQ_COINT3A 0x4000 /* counter 3A overflow interrupt mask */ -#define IRQ_COINT3B 0x8000 /* counter 3B overflow interrupt mask */ +#define S626_IRQ_COINT1A 0x0400 /* counter 1A overflow interrupt mask */ +#define S626_IRQ_COINT1B 0x0800 /* counter 1B overflow interrupt mask */ +#define S626_IRQ_COINT2A 0x1000 /* counter 2A overflow interrupt mask */ +#define S626_IRQ_COINT2B 0x2000 /* counter 2B overflow interrupt mask */ +#define S626_IRQ_COINT3A 0x4000 /* counter 3A overflow interrupt mask */ +#define S626_IRQ_COINT3B 0x8000 /* counter 3B overflow interrupt mask */ /* RPS command codes. */ -#define RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */ -#define RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */ -#define RPS_NOP 0x00000000 /* NOP */ -#define RPS_PAUSE 0x20000000 /* PAUSE */ -#define RPS_UPLOAD 0x40000000 /* UPLOAD */ -#define RPS_JUMP 0x80000000 /* JUMP */ -#define RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */ -#define RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */ -#define RPS_STOP 0x50000000 /* STOP */ -#define RPS_IRQ 0x60000000 /* IRQ */ - -#define RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */ -#define RPS_INVERT 0x04000000 /* Test for negated +#define S626_RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */ +#define S626_RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */ +#define S626_RPS_NOP 0x00000000 /* NOP */ +#define S626_RPS_PAUSE 0x20000000 /* PAUSE */ +#define S626_RPS_UPLOAD 0x40000000 /* UPLOAD */ +#define S626_RPS_JUMP 0x80000000 /* JUMP */ +#define S626_RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */ +#define S626_RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */ +#define S626_RPS_STOP 0x50000000 /* STOP */ +#define S626_RPS_IRQ 0x60000000 /* IRQ */ + +#define S626_RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */ +#define S626_RPS_INVERT 0x04000000 /* Test for negated * semaphores. */ -#define RPS_DEBI 0x00000002 /* DEBI done */ +#define S626_RPS_DEBI 0x00000002 /* DEBI done */ -#define RPS_SIG0 0x00200000 /* RPS semaphore 0 +#define S626_RPS_SIG0 0x00200000 /* RPS semaphore 0 * (used by ADC). */ -#define RPS_SIG1 0x00400000 /* RPS semaphore 1 +#define S626_RPS_SIG1 0x00400000 /* RPS semaphore 1 * (used by DAC). */ -#define RPS_SIG2 0x00800000 /* RPS semaphore 2 +#define S626_RPS_SIG2 0x00800000 /* RPS semaphore 2 * (not used). */ -#define RPS_GPIO2 0x00080000 /* RPS GPIO2 */ -#define RPS_GPIO3 0x00100000 /* RPS GPIO3 */ +#define S626_RPS_GPIO2 0x00080000 /* RPS GPIO2 */ +#define S626_RPS_GPIO3 0x00100000 /* RPS GPIO3 */ -#define RPS_SIGADC RPS_SIG0 /* Trigger/status for +#define S626_RPS_SIGADC S626_RPS_SIG0 /* Trigger/status for * ADC's RPS program. */ -#define RPS_SIGDAC RPS_SIG1 /* Trigger/status for +#define S626_RPS_SIGDAC S626_RPS_SIG1 /* Trigger/status for * DAC's RPS program. */ /* RPS clock parameters. */ -#define RPSCLK_SCALAR 8 /* This is apparent ratio of +#define S626_RPSCLK_SCALAR 8 /* This is apparent ratio of * PCI/RPS clks (undocumented!!). */ -#define RPSCLK_PER_US (33 / RPSCLK_SCALAR) +#define S626_RPSCLK_PER_US (33 / S626_RPSCLK_SCALAR) /* Number of RPS clocks in one * microsecond. */ /* Event counter source addresses. */ -#define SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */ +#define S626_SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */ /* GPIO constants. */ -#define GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, +#define S626_GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, * GPIO3 = IRQ; GPIO1 = out. */ -#define GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */ -#define GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */ +#define S626_GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */ +#define S626_GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */ /* Primary Status Register (PSR) constants. */ -#define PSR_DEBI_E 0x00040000 /* DEBI event flag. */ -#define PSR_DEBI_S 0x00080000 /* DEBI status flag. */ -#define PSR_A2_IN 0x00008000 /* Audio output DMA2 protection +#define S626_PSR_DEBI_E 0x00040000 /* DEBI event flag. */ +#define S626_PSR_DEBI_S 0x00080000 /* DEBI status flag. */ +#define S626_PSR_A2_IN 0x00008000 /* Audio output DMA2 protection * address reached. */ -#define PSR_AFOU 0x00000800 /* Audio FIFO under/overflow +#define S626_PSR_AFOU 0x00000800 /* Audio FIFO under/overflow * detected. */ -#define PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, +#define S626_PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, * 1=AdcIdle. */ -#define PSR_EC0S 0x00000001 /* Event counter 0 threshold +#define S626_PSR_EC0S 0x00000001 /* Event counter 0 threshold * reached. */ /* Secondary Status Register (SSR) constants. */ -#define SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO +#define S626_SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO * under/overflow detected. */ /* Master Control Register 1 (MC1) constants. */ -#define MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */ -#define MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled +#define S626_MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */ +#define S626_MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled * enables. */ -#define MC1_ERPS1 0x2000 /* Enab/disable RPS task 1. */ -#define MC1_ERPS0 0x1000 /* Enab/disable RPS task 0. */ -#define MC1_DEBI 0x0800 /* Enab/disable DEBI pins. */ -#define MC1_AUDIO 0x0200 /* Enab/disable audio port pins. */ -#define MC1_I2C 0x0100 /* Enab/disable I2C interface. */ -#define MC1_A2OUT 0x0008 /* Enab/disable transfer on A2 out. */ -#define MC1_A2IN 0x0004 /* Enab/disable transfer on A2 in. */ -#define MC1_A1IN 0x0001 /* Enab/disable transfer on A1 in. */ +#define S626_MC1_ERPS1 0x2000 /* Enab/disable RPS task 1. */ +#define S626_MC1_ERPS0 0x1000 /* Enab/disable RPS task 0. */ +#define S626_MC1_DEBI 0x0800 /* Enab/disable DEBI pins. */ +#define S626_MC1_AUDIO 0x0200 /* Enab/disable audio port pins. */ +#define S626_MC1_I2C 0x0100 /* Enab/disable I2C interface. */ +#define S626_MC1_A2OUT 0x0008 /* Enab/disable transfer on A2 out. */ +#define S626_MC1_A2IN 0x0004 /* Enab/disable transfer on A2 in. */ +#define S626_MC1_A1IN 0x0001 /* Enab/disable transfer on A1 in. */ /* Master Control Register 2 (MC2) constants. */ -#define MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */ -#define MC2_UPLD_IIC 0x0001 /* Upload I2C. */ -#define MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */ -#define MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */ -#define MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */ +#define S626_MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */ +#define S626_MC2_UPLD_IIC 0x0001 /* Upload I2C. */ +#define S626_MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */ +#define S626_MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */ +#define S626_MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */ -#define MC2_ADC_RPS MC2_RPSSIG0 /* ADC RPS busy. */ -#define MC2_DAC_RPS MC2_RPSSIG1 /* DAC RPS busy. */ +#define S626_MC2_ADC_RPS S626_MC2_RPSSIG0 /* ADC RPS busy. */ +#define S626_MC2_DAC_RPS S626_MC2_RPSSIG1 /* DAC RPS busy. */ /* PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS */ -#define P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */ -#define P_DEBICFG 0x007C /* DEBI configuration. */ -#define P_DEBICMD 0x0080 /* DEBI command. */ -#define P_DEBIPAGE 0x0084 /* DEBI page. */ -#define P_DEBIAD 0x0088 /* DEBI target address. */ -#define P_I2CCTRL 0x008C /* I2C control. */ -#define P_I2CSTAT 0x0090 /* I2C status. */ -#define P_BASEA2_IN 0x00AC /* Audio input 2 base physical DMAbuf +#define S626_P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */ +#define S626_P_DEBICFG 0x007C /* DEBI configuration. */ +#define S626_P_DEBICMD 0x0080 /* DEBI command. */ +#define S626_P_DEBIPAGE 0x0084 /* DEBI page. */ +#define S626_P_DEBIAD 0x0088 /* DEBI target address. */ +#define S626_P_I2CCTRL 0x008C /* I2C control. */ +#define S626_P_I2CSTAT 0x0090 /* I2C status. */ +#define S626_P_BASEA2_IN 0x00AC /* Audio input 2 base physical DMAbuf * address. */ -#define P_PROTA2_IN 0x00B0 /* Audio input 2 physical DMAbuf +#define S626_P_PROTA2_IN 0x00B0 /* Audio input 2 physical DMAbuf * protection address. */ -#define P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */ -#define P_BASEA2_OUT 0x00B8 /* Audio output 2 base physical DMAbuf +#define S626_P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */ +#define S626_P_BASEA2_OUT 0x00B8 /* Audio output 2 base physical DMAbuf * address. */ -#define P_PROTA2_OUT 0x00BC /* Audio output 2 physical DMAbuf +#define S626_P_PROTA2_OUT 0x00BC /* Audio output 2 physical DMAbuf * protection address. */ -#define P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */ -#define P_RPSPAGE0 0x00C4 /* RPS0 page. */ -#define P_RPSPAGE1 0x00C8 /* RPS1 page. */ -#define P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */ -#define P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */ -#define P_IER 0x00DC /* Interrupt enable. */ -#define P_GPIO 0x00E0 /* General-purpose I/O. */ -#define P_EC1SSR 0x00E4 /* Event counter set 1 source select. */ -#define P_ECT1R 0x00EC /* Event counter threshold set 1. */ -#define P_ACON1 0x00F4 /* Audio control 1. */ -#define P_ACON2 0x00F8 /* Audio control 2. */ -#define P_MC1 0x00FC /* Master control 1. */ -#define P_MC2 0x0100 /* Master control 2. */ -#define P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */ -#define P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */ -#define P_ISR 0x010C /* Interrupt status. */ -#define P_PSR 0x0110 /* Primary status. */ -#define P_SSR 0x0114 /* Secondary status. */ -#define P_EC1R 0x0118 /* Event counter set 1. */ -#define P_ADP4 0x0138 /* Logical audio DMA pointer of audio +#define S626_P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */ +#define S626_P_RPSPAGE0 0x00C4 /* RPS0 page. */ +#define S626_P_RPSPAGE1 0x00C8 /* RPS1 page. */ +#define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */ +#define S626_P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */ +#define S626_P_IER 0x00DC /* Interrupt enable. */ +#define S626_P_GPIO 0x00E0 /* General-purpose I/O. */ +#define S626_P_EC1SSR 0x00E4 /* Event counter set 1 source select. */ +#define S626_P_ECT1R 0x00EC /* Event counter threshold set 1. */ +#define S626_P_ACON1 0x00F4 /* Audio control 1. */ +#define S626_P_ACON2 0x00F8 /* Audio control 2. */ +#define S626_P_MC1 0x00FC /* Master control 1. */ +#define S626_P_MC2 0x0100 /* Master control 2. */ +#define S626_P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */ +#define S626_P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */ +#define S626_P_ISR 0x010C /* Interrupt status. */ +#define S626_P_PSR 0x0110 /* Primary status. */ +#define S626_P_SSR 0x0114 /* Secondary status. */ +#define S626_P_EC1R 0x0118 /* Event counter set 1. */ +#define S626_P_ADP4 0x0138 /* Logical audio DMA pointer of audio * input FIFO A2_IN. */ -#define P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */ -#define P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */ -#define P_TSL1 0x0180 /* Audio time slot list 1. */ -#define P_TSL2 0x01C0 /* Audio time slot list 2. */ +#define S626_P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */ +#define S626_P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */ +#define S626_P_TSL1 0x0180 /* Audio time slot list 1. */ +#define S626_P_TSL2 0x01C0 /* Audio time slot list 2. */ /* LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS */ /* Analog I/O registers: */ -#define LP_DACPOL 0x0082 /* Write DAC polarity. */ -#define LP_GSEL 0x0084 /* Write ADC gain. */ -#define LP_ISEL 0x0086 /* Write ADC channel select. */ +#define S626_LP_DACPOL 0x0082 /* Write DAC polarity. */ +#define S626_LP_GSEL 0x0084 /* Write ADC gain. */ +#define S626_LP_ISEL 0x0086 /* Write ADC channel select. */ /* Digital I/O registers */ -#define LP_RDDIN(x) (0x0040 + (x) * 0x10) /* R: digital input */ -#define LP_WRINTSEL(x) (0x0042 + (x) * 0x10) /* W: int enable */ -#define LP_WREDGSEL(x) (0x0044 + (x) * 0x10) /* W: edge selection */ -#define LP_WRCAPSEL(x) (0x0046 + (x) * 0x10) /* W: capture enable */ -#define LP_RDCAPFLG(x) (0x0048 + (x) * 0x10) /* R: edges captured */ -#define LP_WRDOUT(x) (0x0048 + (x) * 0x10) /* W: digital output */ -#define LP_RDINTSEL(x) (0x004a + (x) * 0x10) /* R: int enable */ -#define LP_RDEDGSEL(x) (0x004c + (x) * 0x10) /* R: edge selection */ -#define LP_RDCAPSEL(x) (0x004e + (x) * 0x10) /* R: capture enable */ +#define S626_LP_RDDIN(x) (0x0040 + (x) * 0x10) /* R: digital input */ +#define S626_LP_WRINTSEL(x) (0x0042 + (x) * 0x10) /* W: int enable */ +#define S626_LP_WREDGSEL(x) (0x0044 + (x) * 0x10) /* W: edge selection */ +#define S626_LP_WRCAPSEL(x) (0x0046 + (x) * 0x10) /* W: capture enable */ +#define S626_LP_RDCAPFLG(x) (0x0048 + (x) * 0x10) /* R: edges captured */ +#define S626_LP_WRDOUT(x) (0x0048 + (x) * 0x10) /* W: digital output */ +#define S626_LP_RDINTSEL(x) (0x004a + (x) * 0x10) /* R: int enable */ +#define S626_LP_RDEDGSEL(x) (0x004c + (x) * 0x10) /* R: edge selection */ +#define S626_LP_RDCAPSEL(x) (0x004e + (x) * 0x10) /* R: capture enable */ /* Counter Registers (read/write): */ -#define LP_CR0A 0x0000 /* 0A setup register. */ -#define LP_CR0B 0x0002 /* 0B setup register. */ -#define LP_CR1A 0x0004 /* 1A setup register. */ -#define LP_CR1B 0x0006 /* 1B setup register. */ -#define LP_CR2A 0x0008 /* 2A setup register. */ -#define LP_CR2B 0x000A /* 2B setup register. */ +#define S626_LP_CR0A 0x0000 /* 0A setup register. */ +#define S626_LP_CR0B 0x0002 /* 0B setup register. */ +#define S626_LP_CR1A 0x0004 /* 1A setup register. */ +#define S626_LP_CR1B 0x0006 /* 1B setup register. */ +#define S626_LP_CR2A 0x0008 /* 2A setup register. */ +#define S626_LP_CR2B 0x000A /* 2B setup register. */ /* Counter PreLoad (write) and Latch (read) Registers: */ -#define LP_CNTR0ALSW 0x000C /* 0A lsw. */ -#define LP_CNTR0AMSW 0x000E /* 0A msw. */ -#define LP_CNTR0BLSW 0x0010 /* 0B lsw. */ -#define LP_CNTR0BMSW 0x0012 /* 0B msw. */ -#define LP_CNTR1ALSW 0x0014 /* 1A lsw. */ -#define LP_CNTR1AMSW 0x0016 /* 1A msw. */ -#define LP_CNTR1BLSW 0x0018 /* 1B lsw. */ -#define LP_CNTR1BMSW 0x001A /* 1B msw. */ -#define LP_CNTR2ALSW 0x001C /* 2A lsw. */ -#define LP_CNTR2AMSW 0x001E /* 2A msw. */ -#define LP_CNTR2BLSW 0x0020 /* 2B lsw. */ -#define LP_CNTR2BMSW 0x0022 /* 2B msw. */ +#define S626_LP_CNTR0ALSW 0x000C /* 0A lsw. */ +#define S626_LP_CNTR0AMSW 0x000E /* 0A msw. */ +#define S626_LP_CNTR0BLSW 0x0010 /* 0B lsw. */ +#define S626_LP_CNTR0BMSW 0x0012 /* 0B msw. */ +#define S626_LP_CNTR1ALSW 0x0014 /* 1A lsw. */ +#define S626_LP_CNTR1AMSW 0x0016 /* 1A msw. */ +#define S626_LP_CNTR1BLSW 0x0018 /* 1B lsw. */ +#define S626_LP_CNTR1BMSW 0x001A /* 1B msw. */ +#define S626_LP_CNTR2ALSW 0x001C /* 2A lsw. */ +#define S626_LP_CNTR2AMSW 0x001E /* 2A msw. */ +#define S626_LP_CNTR2BLSW 0x0020 /* 2B lsw. */ +#define S626_LP_CNTR2BMSW 0x0022 /* 2B msw. */ /* Miscellaneous Registers (read/write): */ -#define LP_MISC1 0x0088 /* Read/write Misc1. */ -#define LP_WRMISC2 0x0090 /* Write Misc2. */ -#define LP_RDMISC2 0x0082 /* Read Misc2. */ +#define S626_LP_MISC1 0x0088 /* Read/write Misc1. */ +#define S626_LP_WRMISC2 0x0090 /* Write Misc2. */ +#define S626_LP_RDMISC2 0x0082 /* Read Misc2. */ /* Bit masks for MISC1 register that are the same for reads and writes. */ -#define MISC1_WENABLE 0x8000 /* enab writes to MISC2 (except Clear +#define S626_MISC1_WENABLE 0x8000 /* enab writes to MISC2 (except Clear * Watchdog bit). */ -#define MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */ -#define MISC1_EDCAP 0x1000 /* Enable edge capture on DIO chans - * specified by LP_WRCAPSELx. */ -#define MISC1_NOEDCAP 0x0000 /* Disable edge capture on specified +#define S626_MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */ +#define S626_MISC1_EDCAP 0x1000 /* Enable edge capture on DIO chans + * specified by S626_LP_WRCAPSELx. */ +#define S626_MISC1_NOEDCAP 0x0000 /* Disable edge capture on specified * DIO chans. */ /* Bit masks for MISC1 register reads. */ -#define RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */ +#define S626_RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */ /* Bit masks for MISC2 register writes. */ -#define WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */ -#define WRMISC2_CHARGE_ENABLE 0x4000 /* Enable battery trickle charging. */ +#define S626_WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */ +#define S626_WRMISC2_CHARGE_ENABLE 0x4000 /* Enable battery trickle charging. */ /* Bit masks for MISC2 register that are the same for reads and writes. */ -#define MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */ -#define MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */ -#define MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval select mask. */ +#define S626_MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */ +#define S626_MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */ +#define S626_MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval select mask. */ /* Bit masks for ACON1 register. */ -#define A2_RUN 0x40000000 /* Run A2 based on TSL2. */ -#define A1_RUN 0x20000000 /* Run A1 based on TSL1. */ -#define A1_SWAP 0x00200000 /* Use big-endian for A1. */ -#define A2_SWAP 0x00100000 /* Use big-endian for A2. */ -#define WS_MODES 0x00019999 /* WS0 = TSL1 trigger input, +#define S626_A2_RUN 0x40000000 /* Run A2 based on TSL2. */ +#define S626_A1_RUN 0x20000000 /* Run A1 based on TSL1. */ +#define S626_A1_SWAP 0x00200000 /* Use big-endian for A1. */ +#define S626_A2_SWAP 0x00100000 /* Use big-endian for A2. */ +#define S626_WS_MODES 0x00019999 /* WS0 = TSL1 trigger input, * WS1-WS4 = CS* outputs. */ -#if PLATFORM == INTEL /* Base ACON1 config: always run A1 based - * on TSL1. */ -#define ACON1_BASE (WS_MODES | A1_RUN) -#elif PLATFORM == MOTOROLA -#define ACON1_BASE (WS_MODES | A1_RUN | A1_SWAP | A2_SWAP) +#if S626_PLATFORM == S626_INTEL /* Base ACON1 config: always run + * A1 based on TSL1. */ +#define S626_ACON1_BASE (S626_WS_MODES | S626_A1_RUN) +#elif S626_PLATFORM == S626_MOTOROLA +#define S626_ACON1_BASE \ + (S626_WS_MODES | S626_A1_RUN | S626_A1_SWAP | S626_A2_SWAP) #endif -#define ACON1_ADCSTART ACON1_BASE /* Start ADC: run A1 +#define S626_ACON1_ADCSTART S626_ACON1_BASE /* Start ADC: run A1 * based on TSL1. */ -#define ACON1_DACSTART (ACON1_BASE | A2_RUN) +#define S626_ACON1_DACSTART (S626_ACON1_BASE | S626_A2_RUN) /* Start transmit to DAC: run A2 based on TSL2. */ -#define ACON1_DACSTOP ACON1_BASE /* Halt A2. */ +#define S626_ACON1_DACSTOP S626_ACON1_BASE /* Halt A2. */ /* Bit masks for ACON2 register. */ -#define A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */ -#define A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 +#define S626_A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */ +#define S626_A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 * (DACs). */ -#define A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 +#define S626_A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 * (DACs). */ -#define A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 +#define S626_A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 * (DACs). */ -#define INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */ -#define BCLK2_OE 0x00040000 /* Enable BCLK2 (DACs). */ -#define ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 +#define S626_INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */ +#define S626_BCLK2_OE 0x00040000 /* Enable BCLK2 (DACs). */ +#define S626_ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 * active-low bits. */ -#define ACON2_INIT (ACON2_XORMASK ^ \ - (A1_CLKSRC_BCLK1 | A2_CLKSRC_X2 | \ - INVERT_BCLK2 | BCLK2_OE)) +#define S626_ACON2_INIT (S626_ACON2_XORMASK ^ \ + (S626_A1_CLKSRC_BCLK1 | S626_A2_CLKSRC_X2 | \ + S626_INVERT_BCLK2 | S626_BCLK2_OE)) /* Bit masks for timeslot records. */ -#define WS1 0x40000000 /* WS output to assert. */ -#define WS2 0x20000000 -#define WS3 0x10000000 -#define WS4 0x08000000 -#define RSD1 0x01000000 /* Shift A1 data in on SD1. */ -#define SDW_A1 0x00800000 /* Store rcv'd char at next char +#define S626_WS1 0x40000000 /* WS output to assert. */ +#define S626_WS2 0x20000000 +#define S626_WS3 0x10000000 +#define S626_WS4 0x08000000 +#define S626_RSD1 0x01000000 /* Shift A1 data in on SD1. */ +#define S626_SDW_A1 0x00800000 /* Store rcv'd char at next char * slot of DWORD1 buffer. */ -#define SIB_A1 0x00400000 /* Store rcv'd char at next +#define S626_SIB_A1 0x00400000 /* Store rcv'd char at next * char slot of FB1 buffer. */ -#define SF_A1 0x00200000 /* Write unsigned long +#define S626_SF_A1 0x00200000 /* Write unsigned long * buffer to input FIFO. */ /* Select parallel-to-serial converter's data source: */ -#define XFIFO_0 0x00000000 /* Data fifo byte 0. */ -#define XFIFO_1 0x00000010 /* Data fifo byte 1. */ -#define XFIFO_2 0x00000020 /* Data fifo byte 2. */ -#define XFIFO_3 0x00000030 /* Data fifo byte 3. */ -#define XFB0 0x00000040 /* FB_BUFFER byte 0. */ -#define XFB1 0x00000050 /* FB_BUFFER byte 1. */ -#define XFB2 0x00000060 /* FB_BUFFER byte 2. */ -#define XFB3 0x00000070 /* FB_BUFFER byte 3. */ -#define SIB_A2 0x00000200 /* Store next dword from A2's +#define S626_XFIFO_0 0x00000000 /* Data fifo byte 0. */ +#define S626_XFIFO_1 0x00000010 /* Data fifo byte 1. */ +#define S626_XFIFO_2 0x00000020 /* Data fifo byte 2. */ +#define S626_XFIFO_3 0x00000030 /* Data fifo byte 3. */ +#define S626_XFB0 0x00000040 /* FB_BUFFER byte 0. */ +#define S626_XFB1 0x00000050 /* FB_BUFFER byte 1. */ +#define S626_XFB2 0x00000060 /* FB_BUFFER byte 2. */ +#define S626_XFB3 0x00000070 /* FB_BUFFER byte 3. */ +#define S626_SIB_A2 0x00000200 /* Store next dword from A2's * input shifter to FB2 * buffer. */ -#define SF_A2 0x00000100 /* Store next dword from A2's +#define S626_SF_A2 0x00000100 /* Store next dword from A2's * input shifter to its input * fifo. */ -#define LF_A2 0x00000080 /* Load next dword from A2's +#define S626_LF_A2 0x00000080 /* Load next dword from A2's * output fifo into its * output dword buffer. */ -#define XSD2 0x00000008 /* Shift data out on SD2. */ -#define RSD3 0x00001800 /* Shift data in on SD3. */ -#define RSD2 0x00001000 /* Shift data in on SD2. */ -#define LOW_A2 0x00000002 /* Drive last SD low for 7 clks, +#define S626_XSD2 0x00000008 /* Shift data out on SD2. */ +#define S626_RSD3 0x00001800 /* Shift data in on SD3. */ +#define S626_RSD2 0x00001000 /* Shift data in on SD2. */ +#define S626_LOW_A2 0x00000002 /* Drive last SD low for 7 clks, * then tri-state. */ -#define EOS 0x00000001 /* End of superframe. */ +#define S626_EOS 0x00000001 /* End of superframe. */ /* I2C configuration constants. */ -#define I2C_CLKSEL 0x0400 /* I2C bit rate = +#define S626_I2C_CLKSEL 0x0400 /* I2C bit rate = * PCIclk/480 = 68.75 KHz. */ -#define I2C_BITRATE 68.75 /* I2C bus data bit rate - * (determined by I2C_CLKSEL) - * in KHz. */ -#define I2C_WRTIME 15.0 /* Worst case time, in msec, +#define S626_I2C_BITRATE 68.75 /* I2C bus data bit rate + * (determined by + * S626_I2C_CLKSEL) in KHz. */ +#define S626_I2C_WRTIME 15.0 /* Worst case time, in msec, * for EEPROM internal write * op. */ /* I2C manifest constants. */ /* Max retries to wait for EEPROM write. */ -#define I2C_RETRIES (I2C_WRTIME * I2C_BITRATE / 9.0) -#define I2C_ERR 0x0002 /* I2C control/status flag ERROR. */ -#define I2C_BUSY 0x0001 /* I2C control/status flag BUSY. */ -#define I2C_ABORT 0x0080 /* I2C status flag ABORT. */ -#define I2C_ATTRSTART 0x3 /* I2C attribute START. */ -#define I2C_ATTRCONT 0x2 /* I2C attribute CONT. */ -#define I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */ -#define I2C_ATTRNOP 0x0 /* I2C attribute NOP. */ +#define S626_I2C_RETRIES (S626_I2C_WRTIME * S626_I2C_BITRATE / 9.0) +#define S626_I2C_ERR 0x0002 /* I2C control/status flag ERROR. */ +#define S626_I2C_BUSY 0x0001 /* I2C control/status flag BUSY. */ +#define S626_I2C_ABORT 0x0080 /* I2C status flag ABORT. */ +#define S626_I2C_ATTRSTART 0x3 /* I2C attribute START. */ +#define S626_I2C_ATTRCONT 0x2 /* I2C attribute CONT. */ +#define S626_I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */ +#define S626_I2C_ATTRNOP 0x0 /* I2C attribute NOP. */ /* Code macros used for constructing I2C command bytes. */ -#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) -#define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) -#define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) +#define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) +#define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) +#define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) /* DEBI command constants. */ -#define DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is always +#define S626_DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is always * 2 bytes. */ -#define DEBI_CMD_READ 0x00010000 /* Read operation. */ -#define DEBI_CMD_WRITE 0x00000000 /* Write operation. */ +#define S626_DEBI_CMD_READ 0x00010000 /* Read operation. */ +#define S626_DEBI_CMD_WRITE 0x00000000 /* Write operation. */ /* Read immediate 2 bytes. */ -#define DEBI_CMD_RDWORD (DEBI_CMD_READ | DEBI_CMD_SIZE16) +#define S626_DEBI_CMD_RDWORD (S626_DEBI_CMD_READ | S626_DEBI_CMD_SIZE16) /* Write immediate 2 bytes. */ -#define DEBI_CMD_WRWORD (DEBI_CMD_WRITE | DEBI_CMD_SIZE16) +#define S626_DEBI_CMD_WRWORD (S626_DEBI_CMD_WRITE | S626_DEBI_CMD_SIZE16) /* DEBI configuration constants. */ -#define DEBI_CFG_XIRQ_EN 0x80000000 /* Enable external interrupt +#define S626_DEBI_CFG_XIRQ_EN 0x80000000 /* Enable external interrupt * on GPIO3. */ -#define DEBI_CFG_XRESUME 0x40000000 /* Resume block */ +#define S626_DEBI_CFG_XRESUME 0x40000000 /* Resume block */ /* Transfer when XIRQ * deasserted. */ -#define DEBI_CFG_TOQ 0x03C00000 /* Timeout (15 PCI cycles). */ -#define DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */ +#define S626_DEBI_CFG_TOQ 0x03C00000 /* Timeout (15 PCI cycles). */ +#define S626_DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */ /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */ -#define DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after this many +#define S626_DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after this many * clocks. */ /* 2-bit field that specifies Endian byte lane steering: */ -#define DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't swap any +#define S626_DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't swap any * bytes (Intel). */ -#define DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */ -#define DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */ -#define DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to serve +#define S626_DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */ +#define S626_DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */ +#define S626_DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to serve * 16-bit cycles. */ -#define DEBI_CFG_INC 0x00040000 /* Enable address increment +#define S626_DEBI_CFG_INC 0x00040000 /* Enable address increment * for block transfers. */ -#define DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */ -#define DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */ +#define S626_DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */ +#define S626_DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */ -#if PLATFORM == INTEL +#if S626_PLATFORM == S626_INTEL -#define DEBI_TOUT 7 /* Wait 7 PCI clocks (212 ns) before +#define S626_DEBI_TOUT 7 /* Wait 7 PCI clocks (212 ns) before * polling RDY. */ /* Intel byte lane steering (pass through all byte lanes). */ -#define DEBI_SWAP DEBI_CFG_SWAP_NONE +#define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_NONE -#elif PLATFORM == MOTOROLA +#elif S626_PLATFORM == S626_MOTOROLA -#define DEBI_TOUT 15 /* Wait 15 PCI clocks (454 ns) maximum +#define S626_DEBI_TOUT 15 /* Wait 15 PCI clocks (454 ns) maximum * before timing out. */ /* Motorola byte lane steering. */ -#define DEBI_SWAP DEBI_CFG_SWAP_2 +#define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_2 #endif /* DEBI page table constants. */ -#define DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */ +#define S626_DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */ /* ******* EXTRA FROM OTHER SENSORAY * .h ******* */ /* LoadSrc values: */ -#define LOADSRC_INDX 0 /* Preload core in response to Index. */ -#define LOADSRC_OVER 1 /* Preload core in response to +#define S626_LOADSRC_INDX 0 /* Preload core in response to Index. */ +#define S626_LOADSRC_OVER 1 /* Preload core in response to * Overflow. */ -#define LOADSRCB_OVERA 2 /* Preload B core in response to +#define S626_LOADSRCB_OVERA 2 /* Preload B core in response to * A Overflow. */ -#define LOADSRC_NONE 3 /* Never preload core. */ +#define S626_LOADSRC_NONE 3 /* Never preload core. */ /* IntSrc values: */ -#define INTSRC_NONE 0 /* Interrupts disabled. */ -#define INTSRC_OVER 1 /* Interrupt on Overflow. */ -#define INTSRC_INDX 2 /* Interrupt on Index. */ -#define INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */ +#define S626_INTSRC_NONE 0 /* Interrupts disabled. */ +#define S626_INTSRC_OVER 1 /* Interrupt on Overflow. */ +#define S626_INTSRC_INDX 2 /* Interrupt on Index. */ +#define S626_INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */ /* LatchSrc values: */ -#define LATCHSRC_AB_READ 0 /* Latch on read. */ -#define LATCHSRC_A_INDXA 1 /* Latch A on A Index. */ -#define LATCHSRC_B_INDXB 2 /* Latch B on B Index. */ -#define LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */ +#define S626_LATCHSRC_AB_READ 0 /* Latch on read. */ +#define S626_LATCHSRC_A_INDXA 1 /* Latch A on A Index. */ +#define S626_LATCHSRC_B_INDXB 2 /* Latch B on B Index. */ +#define S626_LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */ /* IndxSrc values: */ -#define INDXSRC_HARD 0 /* Hardware or software index. */ -#define INDXSRC_SOFT 1 /* Software index only. */ +#define S626_INDXSRC_HARD 0 /* Hardware or software index. */ +#define S626_INDXSRC_SOFT 1 /* Software index only. */ /* IndxPol values: */ -#define INDXPOL_POS 0 /* Index input is active high. */ -#define INDXPOL_NEG 1 /* Index input is active low. */ +#define S626_INDXPOL_POS 0 /* Index input is active high. */ +#define S626_INDXPOL_NEG 1 /* Index input is active low. */ /* ClkSrc values: */ -#define CLKSRC_COUNTER 0 /* Counter mode. */ -#define CLKSRC_TIMER 2 /* Timer mode. */ -#define CLKSRC_EXTENDER 3 /* Extender mode. */ +#define S626_CLKSRC_COUNTER 0 /* Counter mode. */ +#define S626_CLKSRC_TIMER 2 /* Timer mode. */ +#define S626_CLKSRC_EXTENDER 3 /* Extender mode. */ /* ClkPol values: */ -#define CLKPOL_POS 0 /* Counter/Extender clock is +#define S626_CLKPOL_POS 0 /* Counter/Extender clock is * active high. */ -#define CLKPOL_NEG 1 /* Counter/Extender clock is +#define S626_CLKPOL_NEG 1 /* Counter/Extender clock is * active low. */ -#define CNTDIR_UP 0 /* Timer counts up. */ -#define CNTDIR_DOWN 1 /* Timer counts down. */ +#define S626_CNTDIR_UP 0 /* Timer counts up. */ +#define S626_CNTDIR_DOWN 1 /* Timer counts down. */ /* ClkEnab values: */ -#define CLKENAB_ALWAYS 0 /* Clock always enabled. */ -#define CLKENAB_INDEX 1 /* Clock is enabled by index. */ +#define S626_CLKENAB_ALWAYS 0 /* Clock always enabled. */ +#define S626_CLKENAB_INDEX 1 /* Clock is enabled by index. */ /* ClkMult values: */ -#define CLKMULT_4X 0 /* 4x clock multiplier. */ -#define CLKMULT_2X 1 /* 2x clock multiplier. */ -#define CLKMULT_1X 2 /* 1x clock multiplier. */ +#define S626_CLKMULT_4X 0 /* 4x clock multiplier. */ +#define S626_CLKMULT_2X 1 /* 2x clock multiplier. */ +#define S626_CLKMULT_1X 2 /* 1x clock multiplier. */ /* Bit Field positions in COUNTER_SETUP structure: */ -#define BF_LOADSRC 9 /* Preload trigger. */ -#define BF_INDXSRC 7 /* Index source. */ -#define BF_INDXPOL 6 /* Index polarity. */ -#define BF_CLKSRC 4 /* Clock source. */ -#define BF_CLKPOL 3 /* Clock polarity/count direction. */ -#define BF_CLKMULT 1 /* Clock multiplier. */ -#define BF_CLKENAB 0 /* Clock enable. */ - -/* - * Enumerated counter operating modes specified by ClkSrc bit field in - * a COUNTER_SETUP. - */ - -#define CLKSRC_COUNTER 0 /* Counter: ENC_C clock, - * ENC_D direction. */ -#define CLKSRC_TIMER 2 /* Timer: SYS_C clock, direction - * specified by ClkPol. */ -#define CLKSRC_EXTENDER 3 /* Extender: OVR_A clock, - * ENC_D direction. */ +#define S626_BF_LOADSRC 9 /* Preload trigger. */ +#define S626_BF_INDXSRC 7 /* Index source. */ +#define S626_BF_INDXPOL 6 /* Index polarity. */ +#define S626_BF_CLKSRC 4 /* Clock source. */ +#define S626_BF_CLKPOL 3 /* Clock polarity/count direction. */ +#define S626_BF_CLKMULT 1 /* Clock multiplier. */ +#define S626_BF_CLKENAB 0 /* Clock enable. */ /* Enumerated counter clock multipliers. */ -#define MULT_X0 0x0003 /* Supports no multipliers; +#define S626_MULT_X0 0x0003 /* Supports no multipliers; * fixed physical multiplier = 3. */ -#define MULT_X1 0x0002 /* Supports multiplier x1; +#define S626_MULT_X1 0x0002 /* Supports multiplier x1; * fixed physical multiplier = 2. */ -#define MULT_X2 0x0001 /* Supports multipliers x1, x2; +#define S626_MULT_X2 0x0001 /* Supports multipliers x1, x2; * physical multipliers = 1 or 2. */ -#define MULT_X4 0x0000 /* Supports multipliers x1, x2, x4; +#define S626_MULT_X4 0x0000 /* Supports multipliers x1, x2, x4; * physical multipliers = 0, 1 or 2. */ /* Sanity-check limits for parameters. */ -#define NUM_COUNTERS 6 /* Maximum valid counter +#define S626_NUM_COUNTERS 6 /* Maximum valid counter * logical channel number. */ -#define NUM_INTSOURCES 4 -#define NUM_LATCHSOURCES 4 -#define NUM_CLKMULTS 4 -#define NUM_CLKSOURCES 4 -#define NUM_CLKPOLS 2 -#define NUM_INDEXPOLS 2 -#define NUM_INDEXSOURCES 2 -#define NUM_LOADTRIGS 4 +#define S626_NUM_INTSOURCES 4 +#define S626_NUM_LATCHSOURCES 4 +#define S626_NUM_CLKMULTS 4 +#define S626_NUM_CLKSOURCES 4 +#define S626_NUM_CLKPOLS 2 +#define S626_NUM_INDEXPOLS 2 +#define S626_NUM_INDEXSOURCES 2 +#define S626_NUM_LOADTRIGS 4 /* Bit field positions in CRA and CRB counter control registers. */ /* Bit field positions in CRA: */ -#define CRABIT_INDXSRC_B 14 /* B index source. */ -#define CRABIT_CLKSRC_B 12 /* B clock source. */ -#define CRABIT_INDXPOL_A 11 /* A index polarity. */ -#define CRABIT_LOADSRC_A 9 /* A preload trigger. */ -#define CRABIT_CLKMULT_A 7 /* A clock multiplier. */ -#define CRABIT_INTSRC_A 5 /* A interrupt source. */ -#define CRABIT_CLKPOL_A 4 /* A clock polarity. */ -#define CRABIT_INDXSRC_A 2 /* A index source. */ -#define CRABIT_CLKSRC_A 0 /* A clock source. */ +#define S626_CRABIT_INDXSRC_B 14 /* B index source. */ +#define S626_CRABIT_CLKSRC_B 12 /* B clock source. */ +#define S626_CRABIT_INDXPOL_A 11 /* A index polarity. */ +#define S626_CRABIT_LOADSRC_A 9 /* A preload trigger. */ +#define S626_CRABIT_CLKMULT_A 7 /* A clock multiplier. */ +#define S626_CRABIT_INTSRC_A 5 /* A interrupt source. */ +#define S626_CRABIT_CLKPOL_A 4 /* A clock polarity. */ +#define S626_CRABIT_INDXSRC_A 2 /* A index source. */ +#define S626_CRABIT_CLKSRC_A 0 /* A clock source. */ /* Bit field positions in CRB: */ -#define CRBBIT_INTRESETCMD 15 /* Interrupt reset command. */ -#define CRBBIT_INTRESET_B 14 /* B interrupt reset enable. */ -#define CRBBIT_INTRESET_A 13 /* A interrupt reset enable. */ -#define CRBBIT_CLKENAB_A 12 /* A clock enable. */ -#define CRBBIT_INTSRC_B 10 /* B interrupt source. */ -#define CRBBIT_LATCHSRC 8 /* A/B latch source. */ -#define CRBBIT_LOADSRC_B 6 /* B preload trigger. */ -#define CRBBIT_CLKMULT_B 3 /* B clock multiplier. */ -#define CRBBIT_CLKENAB_B 2 /* B clock enable. */ -#define CRBBIT_INDXPOL_B 1 /* B index polarity. */ -#define CRBBIT_CLKPOL_B 0 /* B clock polarity. */ +#define S626_CRBBIT_INTRESETCMD 15 /* Interrupt reset command. */ +#define S626_CRBBIT_INTRESET_B 14 /* B interrupt reset enable. */ +#define S626_CRBBIT_INTRESET_A 13 /* A interrupt reset enable. */ +#define S626_CRBBIT_CLKENAB_A 12 /* A clock enable. */ +#define S626_CRBBIT_INTSRC_B 10 /* B interrupt source. */ +#define S626_CRBBIT_LATCHSRC 8 /* A/B latch source. */ +#define S626_CRBBIT_LOADSRC_B 6 /* B preload trigger. */ +#define S626_CRBBIT_CLKMULT_B 3 /* B clock multiplier. */ +#define S626_CRBBIT_CLKENAB_B 2 /* B clock enable. */ +#define S626_CRBBIT_INDXPOL_B 1 /* B index polarity. */ +#define S626_CRBBIT_CLKPOL_B 0 /* B clock polarity. */ /* Bit field masks for CRA and CRB. */ -#define CRAMSK_INDXSRC_B (3 << CRABIT_INDXSRC_B) -#define CRAMSK_CLKSRC_B (3 << CRABIT_CLKSRC_B) -#define CRAMSK_INDXPOL_A (1 << CRABIT_INDXPOL_A) -#define CRAMSK_LOADSRC_A (3 << CRABIT_LOADSRC_A) -#define CRAMSK_CLKMULT_A (3 << CRABIT_CLKMULT_A) -#define CRAMSK_INTSRC_A (3 << CRABIT_INTSRC_A) -#define CRAMSK_CLKPOL_A (3 << CRABIT_CLKPOL_A) -#define CRAMSK_INDXSRC_A (3 << CRABIT_INDXSRC_A) -#define CRAMSK_CLKSRC_A (3 << CRABIT_CLKSRC_A) - -#define CRBMSK_INTRESETCMD (1 << CRBBIT_INTRESETCMD) -#define CRBMSK_INTRESET_B (1 << CRBBIT_INTRESET_B) -#define CRBMSK_INTRESET_A (1 << CRBBIT_INTRESET_A) -#define CRBMSK_CLKENAB_A (1 << CRBBIT_CLKENAB_A) -#define CRBMSK_INTSRC_B (3 << CRBBIT_INTSRC_B) -#define CRBMSK_LATCHSRC (3 << CRBBIT_LATCHSRC) -#define CRBMSK_LOADSRC_B (3 << CRBBIT_LOADSRC_B) -#define CRBMSK_CLKMULT_B (3 << CRBBIT_CLKMULT_B) -#define CRBMSK_CLKENAB_B (1 << CRBBIT_CLKENAB_B) -#define CRBMSK_INDXPOL_B (1 << CRBBIT_INDXPOL_B) -#define CRBMSK_CLKPOL_B (1 << CRBBIT_CLKPOL_B) +#define S626_CRAMSK_INDXSRC_B (3 << S626_CRABIT_INDXSRC_B) +#define S626_CRAMSK_CLKSRC_B (3 << S626_CRABIT_CLKSRC_B) +#define S626_CRAMSK_INDXPOL_A (1 << S626_CRABIT_INDXPOL_A) +#define S626_CRAMSK_LOADSRC_A (3 << S626_CRABIT_LOADSRC_A) +#define S626_CRAMSK_CLKMULT_A (3 << S626_CRABIT_CLKMULT_A) +#define S626_CRAMSK_INTSRC_A (3 << S626_CRABIT_INTSRC_A) +#define S626_CRAMSK_CLKPOL_A (3 << S626_CRABIT_CLKPOL_A) +#define S626_CRAMSK_INDXSRC_A (3 << S626_CRABIT_INDXSRC_A) +#define S626_CRAMSK_CLKSRC_A (3 << S626_CRABIT_CLKSRC_A) + +#define S626_CRBMSK_INTRESETCMD (1 << S626_CRBBIT_INTRESETCMD) +#define S626_CRBMSK_INTRESET_B (1 << S626_CRBBIT_INTRESET_B) +#define S626_CRBMSK_INTRESET_A (1 << S626_CRBBIT_INTRESET_A) +#define S626_CRBMSK_CLKENAB_A (1 << S626_CRBBIT_CLKENAB_A) +#define S626_CRBMSK_INTSRC_B (3 << S626_CRBBIT_INTSRC_B) +#define S626_CRBMSK_LATCHSRC (3 << S626_CRBBIT_LATCHSRC) +#define S626_CRBMSK_LOADSRC_B (3 << S626_CRBBIT_LOADSRC_B) +#define S626_CRBMSK_CLKMULT_B (3 << S626_CRBBIT_CLKMULT_B) +#define S626_CRBMSK_CLKENAB_B (1 << S626_CRBBIT_CLKENAB_B) +#define S626_CRBMSK_INDXPOL_B (1 << S626_CRBBIT_INDXPOL_B) +#define S626_CRBMSK_CLKPOL_B (1 << S626_CRBBIT_CLKPOL_B) /* Interrupt reset control bits. */ -#define CRBMSK_INTCTRL \ - (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A | CRBMSK_INTRESET_B) +#define S626_CRBMSK_INTCTRL (S626_CRBMSK_INTRESETCMD | \ + S626_CRBMSK_INTRESET_A | \ + S626_CRBMSK_INTRESET_B) /* Bit field positions for standardized SETUP structure. */ -#define STDBIT_INTSRC 13 -#define STDBIT_LATCHSRC 11 -#define STDBIT_LOADSRC 9 -#define STDBIT_INDXSRC 7 -#define STDBIT_INDXPOL 6 -#define STDBIT_CLKSRC 4 -#define STDBIT_CLKPOL 3 -#define STDBIT_CLKMULT 1 -#define STDBIT_CLKENAB 0 +#define S626_STDBIT_INTSRC 13 +#define S626_STDBIT_LATCHSRC 11 +#define S626_STDBIT_LOADSRC 9 +#define S626_STDBIT_INDXSRC 7 +#define S626_STDBIT_INDXPOL 6 +#define S626_STDBIT_CLKSRC 4 +#define S626_STDBIT_CLKPOL 3 +#define S626_STDBIT_CLKMULT 1 +#define S626_STDBIT_CLKENAB 0 /* Bit field masks for standardized SETUP structure. */ -#define STDMSK_INTSRC (3 << STDBIT_INTSRC) -#define STDMSK_LATCHSRC (3 << STDBIT_LATCHSRC) -#define STDMSK_LOADSRC (3 << STDBIT_LOADSRC) -#define STDMSK_INDXSRC (1 << STDBIT_INDXSRC) -#define STDMSK_INDXPOL (1 << STDBIT_INDXPOL) -#define STDMSK_CLKSRC (3 << STDBIT_CLKSRC) -#define STDMSK_CLKPOL (1 << STDBIT_CLKPOL) -#define STDMSK_CLKMULT (3 << STDBIT_CLKMULT) -#define STDMSK_CLKENAB (1 << STDBIT_CLKENAB) +#define S626_STDMSK_INTSRC (3 << S626_STDBIT_INTSRC) +#define S626_STDMSK_LATCHSRC (3 << S626_STDBIT_LATCHSRC) +#define S626_STDMSK_LOADSRC (3 << S626_STDBIT_LOADSRC) +#define S626_STDMSK_INDXSRC (1 << S626_STDBIT_INDXSRC) +#define S626_STDMSK_INDXPOL (1 << S626_STDBIT_INDXPOL) +#define S626_STDMSK_CLKSRC (3 << S626_STDBIT_CLKSRC) +#define S626_STDMSK_CLKPOL (1 << S626_STDBIT_CLKPOL) +#define S626_STDMSK_CLKMULT (3 << S626_STDBIT_CLKMULT) +#define S626_STDMSK_CLKENAB (1 << S626_STDBIT_CLKENAB) #endif -- 2.11.0