From d97f3a5ab084485fe4931b6e7d8fa40ae4caa3c1 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Tue, 31 Jul 2012 18:29:21 +0000 Subject: [PATCH] [x86 frame lowering] In 32-bit mode, use ESI as the base pointer. Previously, we were using EBX, but PIC requires the GOT to be in EBX before function calls via PLT GOT pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161066 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86RegisterInfo.cpp | 6 ++++-- test/CodeGen/X86/force-align-stack-alloca.ll | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index acf53f81ffa..a3972b3e3e6 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -72,13 +72,15 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, SlotSize = 8; StackPtr = X86::RSP; FramePtr = X86::RBP; - BasePtr = X86::RBX; } else { SlotSize = 4; StackPtr = X86::ESP; FramePtr = X86::EBP; - BasePtr = X86::EBX; } + // Use a callee-saved register as the base pointer. These registers must + // not conflict with any ABI requirements. For example, in 32-bit mode PIC + // requires GOT in the EBX register before function calls via PLT GOT pointer. + BasePtr = Is64Bit ? X86::RBX : X86::ESI; } /// getCompactUnwindRegNum - This function maps the register to the number for diff --git a/test/CodeGen/X86/force-align-stack-alloca.ll b/test/CodeGen/X86/force-align-stack-alloca.ll index 4ab906797a2..2ada194f891 100644 --- a/test/CodeGen/X86/force-align-stack-alloca.ll +++ b/test/CodeGen/X86/force-align-stack-alloca.ll @@ -24,8 +24,8 @@ define i64 @g(i32 %i) nounwind { ; CHECK-NEXT: andl $-32, %esp ; CHECK-NEXT: subl $32, %esp ; -; Now setup the base pointer (%ebx). -; CHECK-NEXT: movl %esp, %ebx +; Now setup the base pointer (%esi). +; CHECK-NEXT: movl %esp, %esi ; CHECK-NOT: {{[^ ,]*}}, %esp ; ; The next adjustment of the stack is due to the alloca. -- 2.11.0