From da404ab6b50c23ed1c45d775c69c1987a9415be2 Mon Sep 17 00:00:00 2001 From: astoria-d Date: Mon, 15 Aug 2016 23:46:24 +0900 Subject: [PATCH] vram timing debugging... --- de1_nes/de1_nes.vhd | 11 +++--- de1_nes/ppu/ppu.vhd | 41 ++++++++-------------- de1_nes/ppu/ppu_registers.vhd | 21 +++-------- .../modelsim/de1_nes_run_msim_gate_vhdl.do | 33 +++++++++-------- 4 files changed, 43 insertions(+), 63 deletions(-) diff --git a/de1_nes/de1_nes.vhd b/de1_nes/de1_nes.vhd index 3642434..72ffc4c 100644 --- a/de1_nes/de1_nes.vhd +++ b/de1_nes/de1_nes.vhd @@ -151,8 +151,6 @@ architecture rtl of de1_nes is signal dbg_s_oam_addr : out std_logic_vector (4 downto 0); signal dbg_s_oam_data : out std_logic_vector (7 downto 0); - signal dbg_ppu_addr_we_n : out std_logic; - dl_cpu_clk : in std_logic; ppu_clk : in std_logic; vga_clk : in std_logic; @@ -264,7 +262,6 @@ architecture rtl of de1_nes is signal dbg_idl_h, dbg_idl_l : std_logic_vector (7 downto 0); signal dbg_vga_clk : std_logic; - signal dbg_ppu_addr_we_n : std_logic; signal dbg_ppu_addr_dummy : std_logic_vector (13 downto 0); signal dbg_nes_x : std_logic_vector (8 downto 0); signal dbg_vga_x : std_logic_vector (9 downto 0); @@ -311,7 +308,7 @@ begin dbg_exec_cycle_dummy, dbg_ea_carry, dbg_status_dummy, - dbg_pcl, dbg_pch, dbg_sp_dummy, dbg_x, dbg_y, dbg_acc, + dbg_pcl, dbg_pch, dbg_sp_dummy, dbg_x_dummy, dbg_y, dbg_acc, dbg_dec_oe_n, dbg_dec_val, dbg_stat_we_n , @@ -354,7 +351,6 @@ begin dbg_s_oam_ce_rn_wn , dbg_s_oam_addr , dbg_s_oam_data , - dbg_ppu_addr_we_n , cpu_mem_clk , ppu_clk , @@ -421,13 +417,16 @@ begin dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr; dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data; dbg_int_d_bus(4 downto 0) <= dbg_s_oam_addr(4 downto 0); - dbg_ppu_scrl_y <= dbg_s_oam_data; + --dbg_ppu_scrl_y <= dbg_s_oam_data; + dbg_ppu_scrl_y <= dbg_ppu_scrl_y_dummy; dbg_ppu_scrl_x(0) <= ale; dbg_ppu_scrl_x(1) <= rd_n; dbg_ppu_scrl_x(2) <= wr_n; dbg_ppu_scrl_x(3) <= nt0_ce_n; + dbg_sp <= "00" & v_addr(13 downto 8); + dbg_x <= v_addr(7 downto 0); --nmi_n <= dummy_nmi; --------------- diff --git a/de1_nes/ppu/ppu.vhd b/de1_nes/ppu/ppu.vhd index 0281e6f..edaddce 100644 --- a/de1_nes/ppu/ppu.vhd +++ b/de1_nes/ppu/ppu.vhd @@ -25,9 +25,6 @@ entity ppu is signal dbg_s_oam_addr : out std_logic_vector (4 downto 0); signal dbg_s_oam_data : out std_logic_vector (7 downto 0); - signal dbg_ppu_addr_we_n : out std_logic; - - dl_cpu_clk : in std_logic; ppu_clk : in std_logic; vga_clk : in std_logic; @@ -218,7 +215,6 @@ constant WR1 : std_logic_vector (0 downto 0) := "1"; begin - dbg_ppu_ce_n <= ce_n; dbg_ppu_ctrl <= ppu_ctrl; dbg_ppu_mask <= ppu_mask; @@ -226,8 +222,7 @@ begin dbg_ppu_addr <= ppu_addr; dbg_ppu_data <= ppu_data; dbg_ppu_scrl_x <= ppu_scroll_x; - dbg_ppu_scrl_y <= ppu_scroll_y; - dbg_ppu_addr_we_n <= ppu_addr_we_n; + --dbg_ppu_scrl_y <= ppu_scroll_y; ----------------------------- @@ -329,37 +324,34 @@ begin ppu_scroll_y_inst : d_flip_flop generic map(dsize) port map (dl_cpu_clk, rst_n, '1', ppu_scroll_y_we_n, cpu_d, ppu_scroll_y); --- ppu_data_in_inst : d_flip_flop generic map(dsize) --- port map (dl_cpu_clk, rst_n, '1', ppu_data_we_n, vram_ad, ppu_data_in); --- --- ppu_data_out_inst : d_flip_flop generic map(dsize) --- port map (read_data_n, rst_n, '1', '0', ppu_data_in, ppu_data_out); - - ----------------------------- --vram access. ----------------------------- + dbg_ppu_scrl_y(0) <= ppu_addr_upd_n; + dbg_ppu_scrl_y(1) <= ppu_addr_inc_n; + dbg_ppu_scrl_y(2) <= ppu_data_we_n; + ppu_addr_upd_en_inst : d_flip_flop_bit port map (dl_cpu_clk, rst_n, '1', '0', ppu_addr_inc_n, ppu_addr_upd_n); ale <= '1' when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else - '1' when ppu_addr_upd_n = '0' else + --'1' when ppu_addr_upd_n = '0' else '0' when ce_n = '0' and cpu_addr = PPUDATA and r_nw = '0' else 'Z'; wr_n <= '0' when ce_n = '0' and cpu_addr = PPUDATA and r_nw = '0' else - '1' when ppu_addr_upd_n = '0' else + --'1' when ppu_addr_upd_n = '0' else '1' when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else 'Z'; rd_n <= '1' when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else - '1' when ppu_addr_upd_n = '0' else + --'1' when ppu_addr_upd_n = '0' else 'Z'; --- vram_a <= ppu_addr(13 downto 8) when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else --- ppu_addr(13 downto 8) when ppu_addr_upd_n = '0' else --- (others => 'Z'); --- vram_ad <= cpu_d when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else --- ppu_addr(7 downto 0) when ppu_addr_upd_n = '0' else --- cpu_d when ce_n = '0' and cpu_addr = PPUDATA and r_nw = '0' else --- (others => 'Z'); + vram_a <= ppu_addr(13 downto 8) when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else + --ppu_addr(13 downto 8) when ppu_addr_upd_n = '0' else + (others => 'Z'); + vram_ad <= cpu_d when ce_n = '0' and cpu_addr = PPUADDR and r_nw = '0' else + --ppu_addr(7 downto 0) when ppu_addr_upd_n = '0' else + cpu_d when ce_n = '0' and cpu_addr = PPUDATA and r_nw = '0' else + (others => 'Z'); cpu_d <= (others => 'Z'); vblank_n <= 'Z'; @@ -370,9 +362,6 @@ begin g <= (others => 'Z'); b <= (others => 'Z'); - vram_ad <= (others => 'Z'); - vram_a <= (others => 'Z'); - -- vga_render_inst : vga_ppu_render port map ( -- dbg_nes_x , -- dbg_vga_x , diff --git a/de1_nes/ppu/ppu_registers.vhd b/de1_nes/ppu/ppu_registers.vhd index d4cf0c6..db194fe 100644 --- a/de1_nes/ppu/ppu_registers.vhd +++ b/de1_nes/ppu/ppu_registers.vhd @@ -89,27 +89,14 @@ component d_flip_flop ); end component; -component tri_state_buffer - generic ( - dsize : integer := 8 - ); - port ( - oe_n : in std_logic; - d : in std_logic_vector (dsize - 1 downto 0); - q : out std_logic_vector (dsize - 1 downto 0) - ); -end component; - signal d_in : std_logic_vector(13 downto 0); -signal q_out : std_logic_vector(13 downto 0); -signal ale_n : std_logic; +signal we_n : std_logic; begin d_in <= vram_a & vram_ad; - ale_n <= not ale; + we_n <= '0' when ale = '1' else + '1'; out_reg_inst : d_flip_flop generic map (14) - port map (clk, '1', '1', ale_n, d_in, q_out); - tsb_inst : tri_state_buffer generic map (14) - port map (ale, q_out, v_addr); + port map (clk, '1', '1', we_n, d_in, v_addr); end rtl; diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do index 10d0d67..a48cfb3 100644 --- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do +++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do @@ -67,22 +67,27 @@ add wave -label ale sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(0) add wave -label rd_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(1) add wave -label wr_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(2) -add wave -radix hex -label v_addr {sim:/testbench_motones_sim/sim_board/dbg_vram_a(13 downto 8) & - sim:/testbench_motones_sim/sim_board/dbg_vram_ad(7 downto 0)} +add wave -radix hex -label v_addr {sim:/testbench_motones_sim/sim_board/dbg_sp(7 downto 0) & + sim:/testbench_motones_sim/sim_board/dbg_x(7 downto 0)} +add wave -radix hex -label vram_a sim:/testbench_motones_sim/sim_board/dbg_vram_a add wave -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/dbg_vram_ad -add wave -divider oam -add wave -radix hex -label p_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (7 downto 0)} -add wave -radix hex -label p_oam_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (15 downto 8)} -add wave -radix hex -label s_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_int_d_bus (4 downto 0)} -add wave -radix hex -label s_oam_data sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y +add wave -label ppu_data_we_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(2) +add wave -label ppu_addr_inc_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(1) +add wave -label ppu_addr_upd_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(0) -add wave -divider vga_out -add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/v_sync_n -add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/h_sync_n -add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/r -add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/g -add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/b +#add wave -divider oam +#add wave -radix hex -label p_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (7 downto 0)} +#add wave -radix hex -label p_oam_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (15 downto 8)} +#add wave -radix hex -label s_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_int_d_bus (4 downto 0)} +#add wave -radix hex -label s_oam_data sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y +# +#add wave -divider vga_out +#add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/v_sync_n +#add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/h_sync_n +#add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/r +#add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/g +#add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/b view structure @@ -94,4 +99,4 @@ wave zoom full #wave zoom range 3339700 ps 5138320 ps ##wave addcursor 907923400 ps -run 50 us +run 60 us -- 2.11.0