From dc3ad22112de7fe76352ef2aa2943b62eb1836a3 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:44 +0100 Subject: [PATCH] arm64: dts: qcom: sa8775p: add the QUPv3 #2 node Add the second instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-2-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index dc21e8450058..9fbddd980f60 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -499,6 +499,19 @@ }; }; + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x6000>; + ranges; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x5a3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ -- 2.11.0