From defa0afa146f4c2370fe126b7860d6d57cf20909 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <stoklund@2pi.dk>
Date: Mon, 7 May 2012 22:57:55 +0000
Subject: [PATCH] Coalesce subreg-subreg copies.

At least some of them:

  %vreg1:sub_16bit = COPY %vreg2:sub_16bit; GR64:%vreg1, GR32: %vreg2

Previously, we couldn't figure out that the above copy could be
eliminated by coalescing %vreg2 with %vreg1:sub_32bit.

The new getCommonSuperRegClass() hook makes it possible.

This is not very useful yet since the unmodified part of the destination
register usually interferes with the source register. The coalescer
needs to understand sub-register interference checking first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156334 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/RegisterCoalescer.cpp | 39 +++++++++++++++++++++++++--------------
 1 file changed, 25 insertions(+), 14 deletions(-)

diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp
index 567ce1940c9..8ab927ac357 100644
--- a/lib/CodeGen/RegisterCoalescer.cpp
+++ b/lib/CodeGen/RegisterCoalescer.cpp
@@ -258,24 +258,35 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
     }
   } else {
     // Both registers are virtual.
+    const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
+    const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
 
     // Both registers have subreg indices.
     if (SrcSub && DstSub) {
-      // For now we only handle the case of identical indices in commensurate
-      // registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg
-      // FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg.
-      if (SrcSub != DstSub)
+      unsigned SrcPre, DstPre;
+      NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
+                                         SrcPre, DstPre);
+      if (!NewRC)
         return false;
-      const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
-      const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
-      if (!TRI.getCommonSubClass(DstRC, SrcRC))
+
+      // We cannot handle the case where both Src and Dst would be a
+      // sub-register. Yet.
+      if (SrcPre && DstPre) {
+        DEBUG(dbgs() << "\tCannot handle " << NewRC->getName()
+                     << " with subregs " << TRI.getSubRegIndexName(SrcPre)
+                     << " and " << TRI.getSubRegIndexName(DstPre) << '\n');
         return false;
-      SrcSub = DstSub = 0;
+      }
+
+      // One of these will be 0, so one register is a sub-register of the other.
+      SrcSub = DstPre;
+      DstSub = SrcPre;
     }
 
     // There can be no SrcSub.
     if (SrcSub) {
       std::swap(Src, Dst);
+      std::swap(SrcRC, DstRC);
       DstSub = SrcSub;
       SrcSub = 0;
       assert(!Flipped && "Unexpected flip");
@@ -283,12 +294,12 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
     }
 
     // Find the new register class.
-    const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
-    const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
-    if (DstSub)
-      NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
-    else
-      NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
+    if (!NewRC) {
+      if (DstSub)
+        NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
+      else
+        NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
+    }
     if (!NewRC)
       return false;
     CrossClass = NewRC != DstRC || NewRC != SrcRC;
-- 
2.11.0