From df6b5ee0a38af2f4cdaacacbd191a5d87aa6374e Mon Sep 17 00:00:00 2001 From: brolley Date: Thu, 1 Jul 2004 16:55:09 +0000 Subject: [PATCH] 2004-07-01 Dave Brolley * cache.cxx (write_any): Allow misaligned access. Return bus::misaligned for accesses which cross line boundary. (read_any): Ditto. --- sid/component/cache/ChangeLog | 6 ++++++ sid/component/cache/cache.cxx | 29 ++++++++--------------------- 2 files changed, 14 insertions(+), 21 deletions(-) diff --git a/sid/component/cache/ChangeLog b/sid/component/cache/ChangeLog index f3cad5434a..181ae61a94 100644 --- a/sid/component/cache/ChangeLog +++ b/sid/component/cache/ChangeLog @@ -1,3 +1,9 @@ +2004-07-01 Dave Brolley + + * cache.cxx (write_any): Allow misaligned access. Return + bus::misaligned for accesses which cross line boundary. + (read_any): Ditto. + 2004-05-10 Dave Brolley * cacheutil.cxx (find_any_dirty): Make sure the line is valid before diff --git a/sid/component/cache/cache.cxx b/sid/component/cache/cache.cxx index d47f5c5432..932e4c7483 100644 --- a/sid/component/cache/cache.cxx +++ b/sid/component/cache/cache.cxx @@ -183,27 +183,14 @@ cache_component::write_any (host_int_4 addr, DataType data) cache_tag tag = acache.addr_to_tag (addr); if (UNLIKELY (addr % sizeof (data) != 0)) { - // Punt on misaligned accesses if (LIKELY (collect_p)) stats.misaligned_writes++; - - cache_line* line = acache.find (tag); - if (line) - { - if (line->dirty_p ()) - { - // flush a dirty line being replaced - if ((st = write_line (*line)) != bus::ok) - return st; - } - acache.expunge (*line); - } - - st = downstream->read (addr, data); - st.latency += miss_latency; - return st; } + // Punt on access across lines + if (UNLIKELY (addr % line_size + sizeof (data) > line_size)) + return bus::misaligned; + cache_line* line = acache.find (tag); if (LIKELY (line)) { @@ -280,12 +267,12 @@ cache_component::read_any (host_int_4 addr, DataType& data) { if (LIKELY (collect_p)) stats.misaligned_reads++; - - st = downstream->read (addr, data); - st.latency += miss_latency; - return st; } + // Punt on accesses across lines + if (UNLIKELY (addr % line_size + sizeof (data) > line_size)) + return bus::misaligned; + cache_tag tag = acache.addr_to_tag (addr); cache_line* line = acache.find (tag); if (LIKELY (line)) -- 2.11.0