From e10d451e10418f12e72ed8564f22fdba8b10a9b0 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:23 +0100 Subject: [PATCH] arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2 Make sure the SDHCI hardware is properly reset before interacting with it, to protect against any possibly indeterminate state left by the bootloader. Suggested-by: Konrad Dybcio Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Reviewed-by: Luca Weiss Tested-by: Luca Weiss # sm7225-fairphone-fp4 Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-2-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 3a315280c34a..2806194e6959 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -490,6 +490,7 @@ <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd SM6350_CX>; @@ -1068,6 +1069,7 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; -- 2.11.0