From e19c33dbfe95e1807be3eb6f252aa60ad5ace531 Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Tue, 28 Jan 2020 10:06:32 +0100 Subject: [PATCH] dt-bindings: mmc: mmci: add delay block base register for sdmmc To support the sdr104 mode, the sdmmc variant has a hardware delay block to manage the clock phase when sampling data received by the card. This patch adds a second base register (optional) for sdmmc delay block. Signed-off-by: Ludovic Barre Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200128090636.13689-6-ludovic.barre@st.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt index 6d3c626e017d..4ec921e4bf34 100644 --- a/Documentation/devicetree/bindings/mmc/mmci.txt +++ b/Documentation/devicetree/bindings/mmc/mmci.txt @@ -28,6 +28,8 @@ specific for ux500 variant: - st,sig-pin-fbclk : feedback clock signal pin used. specific for sdmmc variant: +- reg : a second base register may be defined if a delay + block is present and used for tuning. - st,sig-dir : signal direction polarity used for cmd, dat0 dat123. - st,neg-edge : data & command phase relation, generated on sd clock falling edge. -- 2.11.0