From e2ff4e489bca62cfb2fb65670cf32c6e5fe27cf8 Mon Sep 17 00:00:00 2001 From: Robin Morisset Date: Wed, 17 Sep 2014 18:09:13 +0000 Subject: [PATCH] Revert "[ARM, Fix] Fix emitLeading/TrailingFence on old ARM processors" It is breaking the build on the buildbots but works fine on my machine, I revert while trying to understand what happens (it appears to depend on the compiler used to build, I probably used a C++11 feature that is not perfectly supported by some of the buildbots). This reverts commit feb3176c4d006f99af8b40373abd56215a90e7cc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217973 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 30 ++++-------------------------- lib/Target/ARM/ARMISelLowering.h | 1 - test/CodeGen/ARM/atomic-load-store.ll | 23 ----------------------- 3 files changed, 4 insertions(+), 50 deletions(-) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index b41d1e3e97a..4195b3bf0a4 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -10984,33 +10984,11 @@ bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; } -Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder, - ARM_MB::MemBOpt Domain) const { +static void makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); - - // First, if the target has no DMB, see what fallback we can use. - if (!Subtarget->hasDataBarrier()) { - // Some ARMv6 cpus can support data barriers with an mcr instruction. - // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get - // here. - if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) { - Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr); - ArrayRef args = {Builder.getInt32(15), Builder.getInt32(0), - Builder.getInt32(0), Builder.getInt32(7), - Builder.getInt32(10), Builder.getInt32(5)}; - return Builder.CreateCall(MCR, args); - } else { - // Instead of using barriers, atomic accesses on these subtargets use - // libcalls. - llvm_unreachable("makeDMB on a target so old that it has no barriers"); - } - } else { - Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb); - // Only a full system barrier exists in the M-class architectures. - Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain; - Constant *CDomain = Builder.getInt32(Domain); - return Builder.CreateCall(DMB, CDomain); - } + Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb); + Constant *CDomain = Builder.getInt32(Domain); + Builder.CreateCall(DMB, CDomain); } // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index d5483553898..aa268f16498 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -393,7 +393,6 @@ namespace llvm { Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override; bool hasLoadLinkedStoreConditional() const override; - Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const; Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override; Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, diff --git a/test/CodeGen/ARM/atomic-load-store.ll b/test/CodeGen/ARM/atomic-load-store.ll index af13dfc80d2..49342d2d1bf 100644 --- a/test/CodeGen/ARM/atomic-load-store.ll +++ b/test/CodeGen/ARM/atomic-load-store.ll @@ -3,8 +3,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO ; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE ; RUN: llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4 -; RUN: llc < %s -mtriple=armv6-apple-ios | FileCheck %s -check-prefix=ARMV6 -; RUN: llc < %s -mtriple=thumbv7m-apple-ios | FileCheck %s -check-prefix=THUMBM define void @test1(i32* %ptr, i32 %val1) { ; ARM-LABEL: test1 @@ -17,14 +15,6 @@ define void @test1(i32* %ptr, i32 %val1) { ; THUMBTWO: dmb {{ish$}} ; THUMBTWO-NEXT: str ; THUMBTWO-NEXT: dmb {{ish$}} -; ARMV6-LABEL: test1 -; ARMV6: mcr p15, #0, {{r[0-9]*}}, c7, c10, #5 -; ARMV6: str -; ARMV6: mcr p15, #0, {{r[0-9]*}}, c7, c10, #5 -; THUMBM-LABEL: test1 -; THUMBM: dmb sy -; THUMBM: str -; THUMBM: dmb sy store atomic i32 %val1, i32* %ptr seq_cst, align 4 ret void } @@ -38,12 +28,6 @@ define i32 @test2(i32* %ptr) { ; THUMBTWO-LABEL: test2 ; THUMBTWO: ldr ; THUMBTWO-NEXT: dmb {{ish$}} -; ARMV6-LABEL: test2 -; ARMV6: ldr -; ARMV6: mcr p15, #0, {{r[0-9]*}}, c7, c10, #5 -; THUMBM-LABEL: test2 -; THUMBM: ldr -; THUMBM: dmb sy %val = load atomic i32* %ptr seq_cst, align 4 ret i32 %val } @@ -71,11 +55,6 @@ define void @test3(i8* %ptr1, i8* %ptr2) { ; THUMBONE-NOT: dmb ; THUMBONE: strb ; THUMBONE-NOT: dmb - -; ARMV6-LABEL: test3 -; ARMV6-NOT: mcr -; THUMBM-LABEL: test3 -; THUMBM-NOT: dmb sy %val = load atomic i8* %ptr1 unordered, align 1 store atomic i8 %val, i8* %ptr2 unordered, align 1 ret void @@ -85,8 +64,6 @@ define void @test4(i8* %ptr1, i8* %ptr2) { ; THUMBONE-LABEL: test4 ; THUMBONE: ___sync_val_compare_and_swap_1 ; THUMBONE: ___sync_lock_test_and_set_1 -; ARMV6-LABEL: test4 -; THUMBM-LABEL: test4 %val = load atomic i8* %ptr1 seq_cst, align 1 store atomic i8 %val, i8* %ptr2 seq_cst, align 1 ret void -- 2.11.0