From e4128eecb4c2c0ed6019ec5798d6d79afba579e6 Mon Sep 17 00:00:00 2001 From: astoria-d Date: Sat, 21 Sep 2013 12:52:22 +0900 Subject: [PATCH] modelsim env set up files clean up. --- de1_nes/.gitignore | 1 - de1_nes/simulation/modelsim/modelsim.ini | 198 +++++++++++++++++++++++++++++++ 2 files changed, 198 insertions(+), 1 deletion(-) create mode 100644 de1_nes/simulation/modelsim/modelsim.ini diff --git a/de1_nes/.gitignore b/de1_nes/.gitignore index 0015c58..a74c71f 100644 --- a/de1_nes/.gitignore +++ b/de1_nes/.gitignore @@ -16,7 +16,6 @@ simulation/modelsim/msim_transcript simulation/modelsim/*.vho simulation/modelsim/*.xrf simulation/modelsim/*.sdo -simulation/modelsim/modelsim.ini simulation/modelsim/vsim.wlf undo_redo.txt *.work diff --git a/de1_nes/simulation/modelsim/modelsim.ini b/de1_nes/simulation/modelsim/modelsim.ini new file mode 100644 index 0000000..2ed395a --- /dev/null +++ b/de1_nes/simulation/modelsim/modelsim.ini @@ -0,0 +1,198 @@ +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera specific primitive library mappings + +work = rtl_work +[vcom] +; Turn on VHDL-1993 as the default. Normally is off. +; VHDL93 = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; .ini file has Explict enable so that std_logic_signed/unsigned +; will match synthesis tools behavior. + Explicit = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = false + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off inclusion of debugging info within design units. Default is to include. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. + +; RequireConfigForAllDefaultBinding = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. Default is to include. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turns on incremental compilation of modules +; Incremental = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; License = plus + +; Stop the simulator after an assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +;CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. For VHDL, PathSeparator = / +; for Verilog, PathSeparator = . +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, or deposit +; or in other terms, fixed, wired or charged. +; DefaultForceKind = freeze + +; If zero, open files when elaborated +; else open files on first read or write +; DelayFileOpen = 0 + +; Control VHDL files opened for write +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control number of VHDL files open concurrently +; This number should always be less then the +; current ulimit setting for max file descriptors +; 0 = unlimited +ConcurrentFileLimit = 40 + +; This controls the number of hierarchical regions displayed as +; part of a signal name shown in the waveform window. The default +; value or a value of zero tells VSIM to display the full name. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit +; packages. +; NumericStdNoWarnings = 1 + +; Control the format of a generate statement label. Don't quote it. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is to be compressed. +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl -- 2.11.0