From e43bd861e8182bd93c54631185e6018fc243aea3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 2 Oct 2016 15:45:15 +0200 Subject: [PATCH] radeonsi: track buffer bind history MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit similar to gl_buffer_object::UsageHistory Reviewed-by: Nicolai Hähnle Reviewed-by: Edward O'Callaghan --- src/gallium/drivers/radeon/r600_buffer_common.c | 1 + src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeonsi/si_descriptors.c | 11 ++++++++++- src/gallium/drivers/radeonsi/si_state.c | 15 +++++++++++---- 4 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c index 784522dd456..228674a02ad 100644 --- a/src/gallium/drivers/radeon/r600_buffer_common.c +++ b/src/gallium/drivers/radeon/r600_buffer_common.c @@ -516,6 +516,7 @@ r600_alloc_buffer_struct(struct pipe_screen *screen, rbuffer->b.b.screen = screen; rbuffer->b.vtbl = &r600_buffer_vtbl; rbuffer->buf = NULL; + rbuffer->bind_history = 0; rbuffer->TC_L2_dirty = false; rbuffer->is_shared = false; util_range_init(&rbuffer->valid_buffer_range); diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 038c7c7dda6..cea1f22c259 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -180,6 +180,7 @@ struct r600_resource { unsigned bo_alignment; enum radeon_bo_domain domains; enum radeon_bo_flag flags; + unsigned bind_history; /* The buffer range which is initialized (with a write transfer, * streamout, DMA, or as a random access target). The rest of diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 3066323180e..066faa1a19b 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -414,7 +414,9 @@ static void si_set_sampler_view(struct si_context *sctx, pipe_sampler_view_reference(&views->views[slot], view); memcpy(desc, rview->state, 8*4); - if (rtex->resource.b.b.target != PIPE_BUFFER) { + if (rtex->resource.b.b.target == PIPE_BUFFER) { + rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW; + } else { bool is_separate_stencil = rtex->db_compatible && rview->is_stencil_sampler; @@ -640,6 +642,7 @@ static void si_set_shader_image(struct si_context *ctx, view->u.buf.size, descs->list + slot * 8); images->compressed_colortex_mask &= ~(1 << slot); + res->bind_history |= PIPE_BIND_SHADER_IMAGE; } else { static const unsigned char swizzle[4] = { 0, 1, 2, 3 }; struct r600_texture *tex = (struct r600_texture *)res; @@ -1032,6 +1035,8 @@ static void si_set_constant_buffer(struct si_context *sctx, } else { pipe_resource_reference(&buffer, input->buffer); va = r600_resource(buffer)->gpu_address + input->buffer_offset; + /* Only track usage for non-user buffers. */ + r600_resource(buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER; } /* Set the descriptor. */ @@ -1157,6 +1162,8 @@ static void si_set_shader_buffers(struct pipe_context *ctx, radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf, buffers->shader_usage, buffers->priority, true); + buf->bind_history |= PIPE_BIND_SHADER_BUFFER; + buffers->enabled_mask |= 1u << slot; descs->dirty_mask |= 1u << slot; sctx->descriptors_dirty |= @@ -1363,6 +1370,8 @@ static void si_set_streamout_targets(struct pipe_context *ctx, buffers->shader_usage, RADEON_PRIO_SHADER_RW_BUFFER, true); + r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT; + buffers->enabled_mask |= 1u << bufidx; } else { /* Clear the descriptor and unset the resource. */ diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 0376693f852..92f8d90a97c 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3304,11 +3304,14 @@ static void si_set_vertex_buffers(struct pipe_context *ctx, for (i = 0; i < count; i++) { const struct pipe_vertex_buffer *src = buffers + i; struct pipe_vertex_buffer *dsti = dst + i; + struct pipe_resource *buf = src->buffer; - pipe_resource_reference(&dsti->buffer, src->buffer); + pipe_resource_reference(&dsti->buffer, buf); dsti->buffer_offset = src->buffer_offset; dsti->stride = src->stride; - r600_context_add_resource_size(ctx, src->buffer); + r600_context_add_resource_size(ctx, buf); + if (buf) + r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER; } } else { for (i = 0; i < count; i++) { @@ -3324,9 +3327,13 @@ static void si_set_index_buffer(struct pipe_context *ctx, struct si_context *sctx = (struct si_context *)ctx; if (ib) { - pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer); + struct pipe_resource *buf = ib->buffer; + + pipe_resource_reference(&sctx->index_buffer.buffer, buf); memcpy(&sctx->index_buffer, ib, sizeof(*ib)); - r600_context_add_resource_size(ctx, ib->buffer); + r600_context_add_resource_size(ctx, buf); + if (buf) + r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER; } else { pipe_resource_reference(&sctx->index_buffer.buffer, NULL); } -- 2.11.0