From ea73d165882f12c7bccb84ce94dd69949629075a Mon Sep 17 00:00:00 2001 From: Jan Vesely Date: Tue, 15 Nov 2016 23:55:15 +0000 Subject: [PATCH] AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument wbinvl.* are vector instruction that do not sue vector registers. v2: check only M?BUF instructions Differential Revision: https://reviews.llvm.org/D26633 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287056 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 4 ++++ test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index 70b7b6b2671..88536289119 100644 --- a/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -400,6 +400,10 @@ int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) { VDataRCID = Desc.OpInfo[VDataIdx].RegClass; if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) { + // There is no hazard if the instruction does not use vector regs + // (like wbinvl1) + if (VDataIdx == -1) + return -1; // For MUBUF/MTBUF instructions this hazard only exists if the // instruction is not using a register in the soffset field. const MachineOperand *SOffset = diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll index cecfcb1bfe7..4e0f3c37f21 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll @@ -7,9 +7,11 @@ declare void @llvm.amdgcn.buffer.wbinvl1.vol() #0 ; GCN-NEXT: ; BB#0: ; CI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00] ; VI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00] -; GCN-NEXT: s_endpgm +; GCN: s_endpgm define void @test_buffer_wbinvl1_vol() #0 { call void @llvm.amdgcn.buffer.wbinvl1.vol() +; This used to crash in hazard recognizer + store i8 0, i8 addrspace(1)* undef, align 1 ret void } -- 2.11.0