From ebbdedf2b3d60f33e4ba9b235deb2f433645b80b Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Fri, 23 Mar 2018 11:00:42 +0000 Subject: [PATCH] [AArch64] Clean-up a few over-eager regexps in models. Patch by Simon Pilgrim That is a slightly modified version of the AArch64 changes from Simon's D44687 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328303 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64SchedA53.td | 4 +-- lib/Target/AArch64/AArch64SchedThunderX2T99.td | 48 +++++++++++++------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/lib/Target/AArch64/AArch64SchedA53.td b/lib/Target/AArch64/AArch64SchedA53.td index 94b90edb25b..f253a4f3e25 100644 --- a/lib/Target/AArch64/AArch64SchedA53.td +++ b/lib/Target/AArch64/AArch64SchedA53.td @@ -230,11 +230,11 @@ def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$") def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>; def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; -def : InstRW<[A53WriteVLD3], (instregex "LD3Threev(2d)$")>; +def : InstRW<[A53WriteVLD3], (instregex "LD3Threev2d$")>; def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>; def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; -def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; +def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev2d_POST$")>; def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>; def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; diff --git a/lib/Target/AArch64/AArch64SchedThunderX2T99.td b/lib/Target/AArch64/AArch64SchedThunderX2T99.td index 943e75ce4a8..44a8d30a2c1 100644 --- a/lib/Target/AArch64/AArch64SchedThunderX2T99.td +++ b/lib/Target/AArch64/AArch64SchedThunderX2T99.td @@ -423,15 +423,15 @@ def : WriteRes { def : InstRW<[WriteI], (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", - "ADC?(W|X)r(i|r|s|x)", "ADCS?(W|X)r(i|r|s|x)", + "ADC(W|X)r", "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", - "SUBS?(W|X)r(i|r|s|x)", "SBC?(W|X)r(i|r|s|x)", - "SBCS?(W|X)r(i|r|s|x)", "CCMN?(W|X)r(i|r|s|x)", - "CCMP?(W|X)r(i|r|s|x)", "CSEL?(W|X)r(i|r|s|x)", - "CSINC?(W|X)r(i|r|s|x)", "CSINV?(W|X)r(i|r|s|x)", - "CSNEG?(W|X)r(i|r|s|x)")>; + "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", + "SBCS(W|X)r", "CCMN(W|X)(i|r)", + "CCMP(W|X)(i|r)", "CSEL(W|X)r", + "CSINC(W|X)r", "CSINV(W|X)r", + "CSNEG(W|X)r")>; def : InstRW<[WriteI], (instrs COPY)>; @@ -445,15 +445,15 @@ def : WriteRes { def : InstRW<[WriteISReg], (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", - "ADC?(W|X)r(i|r|s|x)", "ADCS?(W|X)r(i|r|s|x)", + "ADC(W|X)r", "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", - "SUBS?(W|X)r(i|r|s|x)", "SBC?(W|X)r(i|r|s|x)", - "SBCS?(W|X)r(i|r|s|x)", "CCMN?(W|X)r(i|r|s|x)", - "CCMP?(W|X)r(i|r|s|x)", "CSEL?(W|X)r(i|r|s|x)", - "CSINC?(W|X)r(i|r|s|x)", "CSINV?(W|X)r(i|r|s|x)", - "CSNEG?(W|X)r(i|r|s|x)")>; + "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", + "SBCS(W|X)r", "CCMN(W|X)(i|r)", + "CCMP(W|X)(i|r)", "CSEL(W|X)r", + "CSINC(W|X)r", "CSINV(W|X)r", + "CSNEG(W|X)r")>; def : WriteRes { let Latency = 1; @@ -464,15 +464,15 @@ def : WriteRes { def : InstRW<[WriteIEReg], (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", - "ADC?(W|X)r(i|r|s|x)", "ADCS?(W|X)r(i|r|s|x)", + "ADC(W|X)r", "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", - "SUBS?(W|X)r(i|r|s|x)", "SBC?(W|X)r(i|r|s|x)", - "SBCS?(W|X)r(i|r|s|x)", "CCMN?(W|X)r(i|r|s|x)", - "CCMP?(W|X)r(i|r|s|x)", "CSEL?(W|X)r(i|r|s|x)", - "CSINC?(W|X)r(i|r|s|x)", "CSINV?(W|X)r(i|r|s|x)", - "CSNEG?(W|X)r(i|r|s|x)")>; + "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", + "SBCS(W|X)r", "CCMN(W|X)(i|r)", + "CCMP(W|X)(i|r)", "CSEL(W|X)r", + "CSINC(W|X)r", "CSINV(W|X)r", + "CSNEG(W|X)r")>; // Move immed def : WriteRes { @@ -1147,7 +1147,7 @@ def : InstRW<[THX2T99XWriteFDivSP], (instrs FDIVSrr)>; def : InstRW<[THX2T99XWriteFSqrtSP], (instrs FSQRTSr)>; def : InstRW<[THX2T99XWriteFDivSP], (instregex "^FDIVv.*32$")>; def : InstRW<[THX2T99XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>; -def : InstRW<[THX2T99Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSrr")>; +def : InstRW<[THX2T99Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSr")>; // FP divide, D-form // FP square root, D-form @@ -1155,7 +1155,7 @@ def : InstRW<[THX2T99XWriteFDivDP], (instrs FDIVDrr)>; def : InstRW<[THX2T99XWriteFSqrtDP], (instrs FSQRTDr)>; def : InstRW<[THX2T99XWriteFDivDP], (instregex "^FDIVv.*64$")>; def : InstRW<[THX2T99XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>; -def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDrr")>; +def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>; // FP multiply // FP multiply accumulate @@ -1259,10 +1259,10 @@ def : WriteRes { // ASIMD arith, reduce, 8B/8H // ASIMD arith, reduce, 16B -// ASIMD logical (MOV, MVN, ORN, ORR) +// ASIMD logical (MVN (alias for NOT), ORN, ORR) def : InstRW<[THX2T99Write_5Cyc_F01], - (instregex "^ANDv", "^BICv", "^EORv", "^MOVv", "^MVNv", - "^ORRv", "^ORNv", "^NOTv")>; + (instregex "^ANDv", "^BICv", "^EORv", "^ORRv", "^ORNv", "^NOTv")>; + // ASIMD arith, reduce def : InstRW<[THX2T99Write_10Cyc_F01], (instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>; @@ -1513,7 +1513,7 @@ def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^INSv")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>; // ASIMD move, integer immed -def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv", "^MOVIDv")>; +def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv")>; // ASIMD move, FP immed def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMOVv")>; -- 2.11.0