From ec5c18ff129ffcf993e92f3a3aa2d6abf99a4563 Mon Sep 17 00:00:00 2001 From: Eugene Leviant Date: Tue, 21 Nov 2017 11:01:28 +0000 Subject: [PATCH] [MI scheduler] Fix VADD and VSUB in cortex-a57 model This patch fixes instregex for interger vector add/sub instructions Differential revision: https://reviews.llvm.org/D40254 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318749 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMScheduleA57.td | 4 ++-- test/CodeGen/ARM/cortex-a57-misched-vadd.ll | 26 ++++++++++++++++++++++++++ test/CodeGen/ARM/cortex-a57-misched-vsub.ll | 26 ++++++++++++++++++++++++++ 3 files changed, 54 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/ARM/cortex-a57-misched-vadd.ll create mode 100644 test/CodeGen/ARM/cortex-a57-misched-vsub.ll diff --git a/lib/Target/ARM/ARMScheduleA57.td b/lib/Target/ARM/ARMScheduleA57.td index 525079d12d5..1ed9e14dfcd 100644 --- a/lib/Target/ARM/ARMScheduleA57.td +++ b/lib/Target/ARM/ARMScheduleA57.td @@ -971,9 +971,9 @@ def : InstRW<[A57WriteVABAL, A57ReadVABAL], (instregex "VABAL(s|u)")>; def : InstRW<[A57Write_3cyc_1V], (instregex "VABDL(s|u)")>; // ASIMD arith, basic -def : InstRW<[A57Write_3cyc_1V], (instregex "VADD", "VADDL", "VADDW", +def : InstRW<[A57Write_3cyc_1V], (instregex "VADDv", "VADDL", "VADDW", "VNEG(s8d|s16d|s32d|s8q|s16q|s32q|d|q)", - "VPADDi", "VPADDL", "VSUB", "VSUBL", "VSUBW")>; + "VPADDi", "VPADDL", "VSUBv", "VSUBL", "VSUBW")>; // ASIMD arith, complex def : InstRW<[A57Write_3cyc_1V], (instregex "VABS", "VADDHN", "VHADD", "VHSUB", diff --git a/test/CodeGen/ARM/cortex-a57-misched-vadd.ll b/test/CodeGen/ARM/cortex-a57-misched-vadd.ll new file mode 100644 index 00000000000..eb8d1c85523 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-vadd.ll @@ -0,0 +1,26 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s + +; CHECK-LABEL: addv_i32:BB#0 +; CHECK: SU(8): {{.*}} VADDv4i32 +; CHECK-NEXT: # preds left +; CHECK-NEXT: # succs left +; CHECK-NEXT: # rdefs left +; CHECK-NEXT: Latency : 3 + +define <4 x i32> @addv_i32(<4 x i32>, <4 x i32>) { + %3 = add <4 x i32> %1, %0 + ret <4 x i32> %3 +} + +; CHECK-LABEL: addv_f32:BB#0 +; CHECK: SU(8): {{.*}} VADDfq +; CHECK-NEXT: # preds left +; CHECK-NEXT: # succs left +; CHECK-NEXT: # rdefs left +; CHECK-NEXT: Latency : 5 + +define <4 x float> @addv_f32(<4 x float>, <4 x float>) { + %3 = fadd <4 x float> %0, %1 + ret <4 x float> %3 +} diff --git a/test/CodeGen/ARM/cortex-a57-misched-vsub.ll b/test/CodeGen/ARM/cortex-a57-misched-vsub.ll new file mode 100644 index 00000000000..c3c445d3f0e --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-vsub.ll @@ -0,0 +1,26 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s + +; CHECK-LABEL: subv_i32:BB#0 +; CHECK: SU(8): {{.*}} VSUBv4i32 +; CHECK-NEXT: # preds left +; CHECK-NEXT: # succs left +; CHECK-NEXT: # rdefs left +; CHECK-NEXT: Latency : 3 + +define <4 x i32> @subv_i32(<4 x i32>, <4 x i32>) { + %3 = sub <4 x i32> %1, %0 + ret <4 x i32> %3 +} + +; CHECK-LABEL: subv_f32:BB#0 +; CHECK: SU(8): {{.*}} VSUBfq +; CHECK-NEXT: # preds left +; CHECK-NEXT: # succs left +; CHECK-NEXT: # rdefs left +; CHECK-NEXT: Latency : 5 + +define <4 x float> @subv_f32(<4 x float>, <4 x float>) { + %3 = fsub <4 x float> %0, %1 + ret <4 x float> %3 +} -- 2.11.0