From ec5cc76de0af9c0d158a88a824ec58f98dc241a6 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Tue, 30 Apr 2019 09:24:43 +0000 Subject: [PATCH] [ARM GlobalISel] Widen small shift operands The legalizer was already widening the shift amount. Add tests for that behaviour, and also support widening the shifted value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359542 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMLegalizerInfo.cpp | 1 + .../CodeGen/ARM/GlobalISel/arm-legalize-binops.mir | 121 +++++++++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp index 5ab211b791e..689a77a9d93 100644 --- a/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -90,6 +90,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) .legalFor({{s32, s32}}) + .minScalar(0, s32) .clampScalar(1, s32, s32); bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) || diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-binops.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-binops.mir index b95fe1f9aa5..dfbbdce4fb4 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalize-binops.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-binops.mir @@ -28,6 +28,11 @@ define void @test_lshr_s32() { ret void } define void @test_ashr_s32() { ret void } define void @test_shl_s32() { ret void } + + define void @test_shift_s8() { ret void } + define void @test_shift_s16() { ret void } + define void @test_shift_amount_s8() { ret void } + define void @test_shift_amount_s16() { ret void } ... --- name: test_add_s8 @@ -638,3 +643,119 @@ body: | BX_RET 14, $noreg, implicit $r0 ... +--- +name: test_shift_s8 +# CHECK-LABEL: name: test_shift_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.0: + liveins: $r0, $r1 + + %0(s32) = COPY $r0 + %1(s32) = COPY $r1 + %2(s8) = G_TRUNC %0(s32) + %3(s8) = G_SHL %2, %1(s32) + ; G_SHL with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SHL {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SHL {{%[0-9]+, %[0-9]+}} + %4(s32) = G_SEXT %3(s8) + $r0 = COPY %4(s32) + BX_RET 14, $noreg, implicit $r0 +... +--- +name: test_shift_s16 +# CHECK-LABEL: name: test_shift_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.0: + liveins: $r0, $r1 + + %0(s32) = COPY $r0 + %1(s32) = COPY $r1 + %2(s16) = G_TRUNC %0(s32) + %3(s16) = G_SHL %2, %1(s32) + ; G_SHL with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SHL {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SHL {{%[0-9]+, %[0-9]+}} + %4(s32) = G_SEXT %3(s16) + $r0 = COPY %4(s32) + BX_RET 14, $noreg, implicit $r0 +... +--- +name: test_shift_amount_s8 +# CHECK-LABEL: name: test_shift_amount_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: $r0, $r1 + + %0(s32) = COPY $r0 + %1(s32) = COPY $r1 + %2(s8) = G_TRUNC %0(s32) + %3(s32) = G_SHL %1, %2(s8) + ; G_SHL with s8 amount should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s8) + ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s32) + ; CHECK-NOT: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s8) + $r0 = COPY %3(s32) + BX_RET 14, $noreg, implicit $r0 +... +--- +name: test_shift_amount_s16 +# CHECK-LABEL: name: test_shift_amount_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: $r0, $r1 + + %0(s32) = COPY $r0 + %1(s32) = COPY $r1 + %2(s16) = G_TRUNC %0(s32) + %3(s32) = G_SHL %1, %2(s16) + ; G_SHL with s16 amount should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s16) + ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s32) + ; CHECK-NOT: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}(s16) + $r0 = COPY %3(s32) + BX_RET 14, $noreg, implicit $r0 +... -- 2.11.0