From ec73276204f06b6446a9c9b70173a1c15f6de536 Mon Sep 17 00:00:00 2001 From: Eric Yuen Date: Tue, 26 Aug 2014 17:11:37 +0200 Subject: [PATCH] PCI: tegra: Make sure the PCIe PLL is really reset Depending on the prior state of the controller, the PLL reset may not be pulsed. Clear the register bit and set it after a small delay to ensure that the PLL is really reset. Tested-by: Stephen Warren Signed-off-by: Eric Yuen Signed-off-by: Thierry Reding Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-tegra.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 6329be3d4695..79fd92c969a9 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -849,6 +849,13 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; pads_writel(pcie, value, soc->pads_pll_ctl); + /* reset PLL */ + value = pads_readl(pcie, soc->pads_pll_ctl); + value &= ~PADS_PLL_CTL_RST_B4SM; + pads_writel(pcie, value, soc->pads_pll_ctl); + + usleep_range(20, 100); + /* take PLL out of reset */ value = pads_readl(pcie, soc->pads_pll_ctl); value |= PADS_PLL_CTL_RST_B4SM; -- 2.11.0