From ed0b86a90bf91d0c41f6b373befd2ce98658b49e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 12:10:42 +1000 Subject: [PATCH] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_curs_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 20 +++++++++++++------- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 17 ++++++++++++----- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 16 +++++++++++----- drivers/gpu/drm/nouveau/dispnv50/head917d.c | 10 ++++++---- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 24 ++++++++++++++++++------ 5 files changed, 60 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index dc50032711b5..473119804b5b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -137,10 +137,16 @@ head507d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 3))) return ret; - PUSH_NVSQ(push, NV507D, 0x0880 + (i * 0x400), 0x80000000 | - asyh->curs.layout << 26 | - asyh->curs.format << 24, - 0x0884 + (i * 0x400), asyh->curs.offset >> 8); + PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | + NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | + NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | + NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) | + NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) | + NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) | + NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE), + + HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); return 0; } @@ -149,7 +155,7 @@ head507d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw, struct nv50_head_atom *asyh) { switch (asyw->image.format) { - case 0xcf: asyh->curs.format = 1; break; + case 0xcf: asyh->curs.format = NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8; break; default: WARN_ON(1); return -EINVAL; @@ -162,8 +168,8 @@ head507d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw, struct nv50_head_atom *asyh) { switch (asyw->image.w) { - case 32: asyh->curs.layout = 0; break; - case 64: asyh->curs.layout = 1; break; + case 32: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break; + case 64: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 1b68c9b82f5a..0dc04774d3d2 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -51,11 +51,18 @@ head827d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NV827D, 0x0880 + (i * 0x400), 0x80000000 | - asyh->curs.layout << 26 | - asyh->curs.format << 24, - 0x0884 + (i * 0x400), asyh->curs.offset >> 8); - PUSH_NVSQ(push, NV827D, 0x089c + (i * 0x400), asyh->curs.handle); + PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | + NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | + NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | + NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) | + NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) | + NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) | + NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE), + + HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); + + PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index f5e669deed62..aca4da6c2eea 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -166,11 +166,17 @@ head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x80000000 | - asyh->curs.layout << 26 | - asyh->curs.format << 24, - 0x0484 + (i * 0x300), asyh->curs.offset >> 8); - PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), asyh->curs.handle); + PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | + NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | + NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | + NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) | + NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) | + NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND), + + HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); + + PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head917d.c b/drivers/gpu/drm/nouveau/dispnv50/head917d.c index 07d12f3ba333..e70628b8d733 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head917d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head917d.c @@ -24,6 +24,8 @@ #include +#include + static int head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -73,10 +75,10 @@ head917d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw, struct nv50_head_atom *asyh) { switch (asyw->state.fb->width) { - case 32: asyh->curs.layout = 0; break; - case 64: asyh->curs.layout = 1; break; - case 128: asyh->curs.layout = 2; break; - case 256: asyh->curs.layout = 3; break; + case 32: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break; + case 64: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break; + case 128: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128; break; + case 256: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256; break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 8898b65d0c41..a9ede937222d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -116,12 +116,24 @@ headc37d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 7))) return ret; - PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x80000000 | - asyh->curs.layout << 8 | - asyh->curs.format << 0, - 0x20a0 + (i * 0x400), 0x000072ff); - PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), asyh->curs.handle); - PUSH_NVSQ(push, NVC37D, 0x2090 + (i * 0x400), asyh->curs.offset >> 8); + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) | + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) | + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, DE_GAMMA, NONE), + + HEAD_SET_CONTROL_CURSOR_COMPOSITION(i), + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, K1, 0xff) | + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, CURSOR_COLOR_FACTOR_SELECT, + K1) | + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, VIEWPORT_COLOR_FACTOR_SELECT, + NEG_K1_TIMES_SRC) | + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND)); + + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle); + PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8); return 0; } -- 2.11.0