From ed2876e520bbdf295f894c5fb7c5a58bf90bf60f Mon Sep 17 00:00:00 2001 From: Udayan Banerji Date: Fri, 29 Mar 2013 14:05:18 -0700 Subject: [PATCH] [x86] Fix errors with WITH_JIT_TUNING defined This patch makes the necessary changes to pass on correct information to dvmBumpNoChain, so that WITH_JIT_TUNING flag can be enabled for x86 codegen Signed-off-by: Udayan Banerji (cherry picked from commit 19eb287ac848f10e03ca2614bf53bd9d1ddd3724) Change-Id: I6871dd0839b3656beed4633e3a0f3df780af98a0 --- vm/compiler/codegen/x86/CodegenInterface.cpp | 8 +++++++- vm/compiler/codegen/x86/LowerInvoke.cpp | 11 +++++++++++ vm/compiler/codegen/x86/LowerJump.cpp | 14 ++++++++++++++ vm/compiler/codegen/x86/LowerReturn.cpp | 6 +++++- vm/mterp/out/InterpAsm-x86.S | 8 ++++++++ vm/mterp/x86/footer.S | 8 ++++++++ 6 files changed, 53 insertions(+), 2 deletions(-) diff --git a/vm/compiler/codegen/x86/CodegenInterface.cpp b/vm/compiler/codegen/x86/CodegenInterface.cpp index 0f516b311..46f097971 100644 --- a/vm/compiler/codegen/x86/CodegenInterface.cpp +++ b/vm/compiler/codegen/x86/CodegenInterface.cpp @@ -327,7 +327,7 @@ static bool inlineCachePatchEnqueue(PredictedChainingCell *cellAddr, cellAddr->clazz = newContent->clazz; //cacheflush((intptr_t) cellAddr, (intptr_t) (cellAddr+1), 0); #endif -#if defined(IA_JIT_TUNING) +#if defined(WITH_JIT_TUNING) gDvmJit.icPatchInit++; #endif COMPILER_TRACE_CHAINING( @@ -720,6 +720,12 @@ static void handleInvokePredictedChainingCell(CompilationUnit *cUnit, int blockI #ifndef PREDICTED_CHAINING //assume rPC for callee->insns in %ebx scratchRegs[0] = PhysicalReg_EAX; +#if defined(WITH_JIT_TUNING) + /* Predicted chaining is not enabled. Fall back to interpreter and + * indicate that predicted chaining was not done. + */ + move_imm_to_reg(OpndSize_32, kInlineCacheMiss, PhysicalReg_EDX, true); +#endif call_dvmJitToInterpTraceSelectNoChain(); #else /* make sure section for predicited chaining cell is 4-byte aligned */ diff --git a/vm/compiler/codegen/x86/LowerInvoke.cpp b/vm/compiler/codegen/x86/LowerInvoke.cpp index 3d02190fa..10bc197f1 100644 --- a/vm/compiler/codegen/x86/LowerInvoke.cpp +++ b/vm/compiler/codegen/x86/LowerInvoke.cpp @@ -833,6 +833,12 @@ int common_invokeArgsDone(ArgsDoneType form, bool isJitFull) { if(callNoChain) { scratchRegs[0] = PhysicalReg_EAX; load_effective_addr(8, PhysicalReg_ESP, true, PhysicalReg_ESP, true); +#if defined(WITH_JIT_TUNING) + /* Predicted chaining failed. Fall back to interpreter and indicate + * inline cache miss. + */ + move_imm_to_reg(OpndSize_32, kInlineCacheMiss, PhysicalReg_EDX, true); +#endif call_dvmJitToInterpTraceSelectNoChain(); //input: rPC in %ebx } else { //jump to the stub at (%esp) @@ -906,6 +912,11 @@ void generate_invokeNative(bool generateForNcg) { //move rPC by 6 (3 bytecode units for INVOKE) alu_binary_imm_reg(OpndSize_32, add_opc, 6, PhysicalReg_EBX, true); scratchRegs[0] = PhysicalReg_EAX; +#if defined(WITH_JIT_TUNING) + /* Return address not in code cache. Indicate that continuing with interpreter + */ + move_imm_to_reg(OpndSize_32, kCallsiteInterpreted, PhysicalReg_EDX, true); +#endif call_dvmJitToInterpTraceSelectNoChain(); //rPC in %ebx } return; diff --git a/vm/compiler/codegen/x86/LowerJump.cpp b/vm/compiler/codegen/x86/LowerJump.cpp index 2b10d6bbf..d4b0df3ef 100644 --- a/vm/compiler/codegen/x86/LowerJump.cpp +++ b/vm/compiler/codegen/x86/LowerJump.cpp @@ -1163,6 +1163,13 @@ int op_packed_switch() { //get rPC, %eax has the relative PC offset alu_binary_imm_reg(OpndSize_32, add_opc, (int)rPC, PhysicalReg_EAX, true); scratchRegs[0] = PhysicalReg_SCRATCH_2; +#if defined(WITH_JIT_TUNING) + /* Fall back to interpreter after resolving address of switch target. + * Indicate a kSwitchOverflow. Note: This is not an "overflow". But it helps + * count the times we return from a Switch + */ + move_imm_to_mem(OpndSize_32, kSwitchOverflow, 0, PhysicalReg_ESP, true); +#endif jumpToInterpNoChain(); rPC += 3; return 0; @@ -1220,6 +1227,13 @@ int op_sparse_switch() { //get rPC, %eax has the relative PC offset alu_binary_imm_reg(OpndSize_32, add_opc, (int)rPC, PhysicalReg_EAX, true); scratchRegs[0] = PhysicalReg_SCRATCH_2; +#if defined(WITH_JIT_TUNING) + /* Fall back to interpreter after resolving address of switch target. + * Indicate a kSwitchOverflow. Note: This is not an "overflow". But it helps + * count the times we return from a Switch + */ + move_imm_to_mem(OpndSize_32, kSwitchOverflow, 0, PhysicalReg_ESP, true); +#endif jumpToInterpNoChain(); rPC += 3; return 0; diff --git a/vm/compiler/codegen/x86/LowerReturn.cpp b/vm/compiler/codegen/x86/LowerReturn.cpp index 928c05c9f..294d6b59d 100644 --- a/vm/compiler/codegen/x86/LowerReturn.cpp +++ b/vm/compiler/codegen/x86/LowerReturn.cpp @@ -95,7 +95,11 @@ int common_returnFromMethod() { typedef void (*vmHelper)(int); vmHelper funcPtr = dvmJitToInterpNoChainNoProfile; //%eax is the input move_imm_to_reg(OpndSize_32, (int)funcPtr, C_SCRATCH_1, isScratchPhysical); - +#if defined(WITH_JIT_TUNING) + /* Return address not in code cache. Indicate that continuing with interpreter. + */ + move_imm_to_mem(OpndSize_32, kCallsiteInterpreted, 0, PhysicalReg_ESP, true); +#endif unconditional_jump_reg(C_SCRATCH_1, isScratchPhysical); touchEax(); return 0; diff --git a/vm/mterp/out/InterpAsm-x86.S b/vm/mterp/out/InterpAsm-x86.S index 760e6740b..c87f30673 100644 --- a/vm/mterp/out/InterpAsm-x86.S +++ b/vm/mterp/out/InterpAsm-x86.S @@ -15754,7 +15754,9 @@ dvmJitToInterpSingleStep: */ dvmJitToInterpNoChainNoProfile: #if defined(WITH_JIT_TUNING) + SPILL_TMP1(%eax) call dvmBumpNoChain + UNSPILL_TMP1(%eax) #endif movl %eax, rPC movl rSELF, %eax @@ -15782,6 +15784,7 @@ dvmJitToInterpNoChainNoProfile: .global dvmJitToInterpTraceSelectNoChain dvmJitToInterpTraceSelectNoChain: #if defined(WITH_JIT_TUNING) + movl %edx, OUT_ARG0(%esp) call dvmBumpNoChain #endif movl %ebx, rPC @@ -15895,6 +15898,11 @@ dvmJitToInterpNormal: .global dvmJitToInterpNoChain dvmJitToInterpNoChain: dvmJitToInterpNoChain: #rPC in eax +#if defined(WITH_JIT_TUNING) + SPILL_TMP1(%eax) + call dvmBumpNoChain + UNSPILL_TMP1(%eax) +#endif ## TODO, need to clean up stack manipulation ... this isn't signal safe and ## doesn't use the calling conventions of header.S movl %eax, rPC diff --git a/vm/mterp/x86/footer.S b/vm/mterp/x86/footer.S index 3b5c79e70..054dc1112 100644 --- a/vm/mterp/x86/footer.S +++ b/vm/mterp/x86/footer.S @@ -77,7 +77,9 @@ dvmJitToInterpSingleStep: */ dvmJitToInterpNoChainNoProfile: #if defined(WITH_JIT_TUNING) + SPILL_TMP1(%eax) call dvmBumpNoChain + UNSPILL_TMP1(%eax) #endif movl %eax, rPC movl rSELF, %eax @@ -105,6 +107,7 @@ dvmJitToInterpNoChainNoProfile: .global dvmJitToInterpTraceSelectNoChain dvmJitToInterpTraceSelectNoChain: #if defined(WITH_JIT_TUNING) + movl %edx, OUT_ARG0(%esp) call dvmBumpNoChain #endif movl %ebx, rPC @@ -218,6 +221,11 @@ dvmJitToInterpNormal: .global dvmJitToInterpNoChain dvmJitToInterpNoChain: dvmJitToInterpNoChain: #rPC in eax +#if defined(WITH_JIT_TUNING) + SPILL_TMP1(%eax) + call dvmBumpNoChain + UNSPILL_TMP1(%eax) +#endif ## TODO, need to clean up stack manipulation ... this isn't signal safe and ## doesn't use the calling conventions of header.S movl %eax, rPC -- 2.11.0