From ed992c96ced5801b9df0d43670bf0405404f7ba9 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 22 Apr 2019 06:12:02 +0000 Subject: [PATCH] [X86] Reject 512-bit types in getRegForInlineAsmConstraint when AVX512 is not enabled. Same for 256 bit and AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358872 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 21b412c987a..2534948bb5c 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -43676,7 +43676,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, // Scalar SSE types. case MVT::f32: case MVT::i32: - if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX()) + if (VConstraint && Subtarget.hasVLX()) return std::make_pair(0U, &X86::FR32XRegClass); return std::make_pair(0U, &X86::FR32RegClass); case MVT::f64: @@ -43704,11 +43704,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case MVT::v4f64: if (VConstraint && Subtarget.hasVLX()) return std::make_pair(0U, &X86::VR256XRegClass); - return std::make_pair(0U, &X86::VR256RegClass); + if (Subtarget.hasAVX()) + return std::make_pair(0U, &X86::VR256RegClass); + break; case MVT::v8f64: case MVT::v16f32: case MVT::v16i32: case MVT::v8i64: + if (!Subtarget.hasAVX512()) break; if (VConstraint) return std::make_pair(0U, &X86::VR512RegClass); return std::make_pair(0U, &X86::VR512_0_15RegClass); -- 2.11.0