From ee46f3c7d79c334e8bdc9947503e329dc27c0b47 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 30 Jun 2015 16:10:38 +0300 Subject: [PATCH] drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel() Similarly to what is done for SKL, clear the dpll_hw_state of the pipe config in hsw_dp_set_ddi_pll_sel(), since it main contain stale values. That can happen if a crtc that was previously driving an HDMI connector switches to a DP connector. In that case, the wrpll field was left with its old value, leading to warnings like the one below: [drm:check_crtc_state [i915]] *ERROR* mismatch in dpll_hw_state.wrpll (expected 0xb035061f, found 0x00000000) ------------[ cut here ]------------ WARNING: CPU: 1 PID: 767 at drivers/gpu/drm/i915/intel_display.c:12324 check_crtc_state+0x975/0x10b0 [i915]() pipe state doesn't match! This regression was indroduced in commit dd3cd74acf12723045a64f1f2c6298ac7b34a5d5 Author: Ander Conselvan de Oliveira Date: Fri May 15 13:34:29 2015 +0300 drm/i915: Don't overwrite (e)DP PLL selection on SKL Reported-by: Linus Torvalds Signed-off-by: Ander Conselvan de Oliveira Tested-by: Jani Nikula Reviewed-by: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 280c282da9bd..16c86ce942ea 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1141,6 +1141,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) static void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw) { + memset(&pipe_config->dpll_hw_state, 0, + sizeof(pipe_config->dpll_hw_state)); + switch (link_bw) { case DP_LINK_BW_1_62: pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; -- 2.11.0