From ef668f2790e966c43ff7e13cbedce98ff9da1f7b Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Sun, 11 Jul 2021 14:53:51 +0800 Subject: [PATCH] drm/mediatek: Adjust rdma fifo threshold calculate formula The orginal formula will caused rdma fifo threshold config overflow and no one could come out a solution for all SoC, set threshold to 70% of max fifo size to make sure it will not overflow, and 70% is a empirical vlaue. Signed-off-by: Yongqiang Niu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 705f28ceb4dd..75d7f45579e2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -162,10 +162,10 @@ void mtk_rdma_config(struct device *dev, unsigned int width, /* * Enable FIFO underflow since DSI and DPI can't be blocked. * Keep the FIFO pseudo size reset default of 8 KiB. Set the - * output threshold to 6 microseconds with 7/6 overhead to - * account for blanking, and with a pixel depth of 4 bytes: + * output threshold to 70% of max fifo size to make sure the + * threhold will not overflow */ - threshold = width * height * vrefresh * 4 * 7 / 1000000; + threshold = rdma_fifo_size * 7 / 10; reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); -- 2.11.0