From ef844758efad67ee7d2cf4b7bc4ce5ec3f2ecbcd Mon Sep 17 00:00:00 2001 From: astoria-d Date: Thu, 19 Sep 2013 18:17:15 +0900 Subject: [PATCH] clock driver fixed --- simulation/clock/clock_divider.vhd | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/simulation/clock/clock_divider.vhd b/simulation/clock/clock_divider.vhd index a890264..8820b7f 100644 --- a/simulation/clock/clock_divider.vhd +++ b/simulation/clock/clock_divider.vhd @@ -54,8 +54,9 @@ begin ppu_clk <= not loop2(0); vga_clk <= base_clk; - cpu_we_n <= '0' when loop6 = "011" else - '1'; + cpu_we_n <= '0' when loop6 = "001" else + '0' when loop6 = "100" else + '1'; ppu_clk_cnt : counter_register generic map (1) port map (base_clk, reset_n, '0', '1', (others=>'0'), loop2); @@ -69,11 +70,13 @@ begin begin if (reset_n = '0') then cpu_cnt_rst_n <= '0'; - elsif (base_clk'event and base_clk = '1') then - if (loop6 = "101") then - cpu_cnt_rst_n <= '0'; - else - cpu_cnt_rst_n <= '1'; + else + if (base_clk'event and base_clk = '1') then + if (loop6 = "101") then + cpu_cnt_rst_n <= '0'; + else + cpu_cnt_rst_n <= '1'; + end if; end if; end if; end process; -- 2.11.0