From efb1cd4c283f830682b51ad92794022156f79f40 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 31 Oct 2017 16:06:21 +0000 Subject: [PATCH] [X86][SSE] Add VSRLI/VSRAI/VSLLI demanded elts support to computeKnownBits/ComputeNumSignBits Mainly a perf improvements as most combines will have occurred before we lower to these instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317005 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 120efaec329..11fe0eae39a 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -27330,7 +27330,7 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op, break; } - DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1); + DAG.computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1); unsigned ShAmt = ShiftImm->getZExtValue(); if (Opc == X86ISD::VSHLI) { Known.Zero <<= ShAmt; @@ -27347,6 +27347,7 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op, break; } case X86ISD::VZEXT: { + // TODO: Add DemandedElts support. SDValue N0 = Op.getOperand(0); unsigned NumElts = VT.getVectorNumElements(); @@ -27396,6 +27397,7 @@ unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode( return VTBits; case X86ISD::VSEXT: { + // TODO: Add DemandedElts support. SDValue Src = Op.getOperand(0); unsigned Tmp = DAG.ComputeNumSignBits(Src, Depth + 1); Tmp += VTBits - Src.getScalarValueSizeInBits(); @@ -27403,6 +27405,7 @@ unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode( } case X86ISD::VTRUNC: { + // TODO: Add DemandedElts support. SDValue Src = Op.getOperand(0); unsigned NumSrcBits = Src.getScalarValueSizeInBits(); assert(VTBits < NumSrcBits && "Illegal truncation input type"); @@ -27425,24 +27428,22 @@ unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode( } case X86ISD::VSHLI: { - // TODO: Add DemandedElts support. SDValue Src = Op.getOperand(0); APInt ShiftVal = cast(Op.getOperand(1))->getAPIntValue(); if (ShiftVal.uge(VTBits)) return VTBits; // Shifted all bits out --> zero. - unsigned Tmp = DAG.ComputeNumSignBits(Src, Depth + 1); + unsigned Tmp = DAG.ComputeNumSignBits(Src, DemandedElts, Depth + 1); if (ShiftVal.uge(Tmp)) return 1; // Shifted all sign bits out --> unknown. return Tmp - ShiftVal.getZExtValue(); } case X86ISD::VSRAI: { - // TODO: Add DemandedElts support. SDValue Src = Op.getOperand(0); APInt ShiftVal = cast(Op.getOperand(1))->getAPIntValue(); if (ShiftVal.uge(VTBits - 1)) return VTBits; // Sign splat. - unsigned Tmp = DAG.ComputeNumSignBits(Src, Depth + 1); + unsigned Tmp = DAG.ComputeNumSignBits(Src, DemandedElts, Depth + 1); ShiftVal += Tmp; return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue(); } -- 2.11.0