From f00123ef4663149675b45abf135b553ebc5e8b0b Mon Sep 17 00:00:00 2001 From: yujiro_kaeko Date: Sat, 6 Aug 2011 14:52:20 +0900 Subject: [PATCH] =?utf8?q?vga=5Fram=E8=A8=AD=E8=A8=88=E5=AE=8C=E4=BA=86FIF?= =?utf8?q?O=20=E3=83=A2=E3=83=8E=E3=82=AF=E3=83=AD=E3=83=87=E3=82=A3?= =?utf8?q?=E3=82=B9=E3=83=97=E3=83=AC=E3=82=A4=E5=AF=BE=E5=BF=9C=20?= =?utf8?q?=EF=BC=98=E8=89=B2=E3=83=87=E3=82=A3=E3=82=B9=E3=83=97=E3=83=AC?= =?utf8?q?=E3=82=A4=E5=AF=BE=E5=BF=9C?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit 4096色ディスプレイ対応可能な設計 4096色の実装はのちほど。 Change-Id: Ib7269297cad3405832ef98ff5198ba0f3a049446 --- VGADisplay/Verilog/FIFO.v | 13 ---------- VGADisplay/Verilog/vga_gen.v | 43 ++++++++++++++++++++++++++++--- VGADisplay/src/vga_gen.nsl | 48 ++++++++++++++++++++++++---------- VGADisplay/src/vga_ram.nsh | 8 +++--- VGADisplay/src/vga_ram.v | 61 +++++++++++++++++++++++--------------------- 5 files changed, 111 insertions(+), 62 deletions(-) delete mode 100644 VGADisplay/Verilog/FIFO.v diff --git a/VGADisplay/Verilog/FIFO.v b/VGADisplay/Verilog/FIFO.v deleted file mode 100644 index 7fa7dff..0000000 --- a/VGADisplay/Verilog/FIFO.v +++ /dev/null @@ -1,13 +0,0 @@ -/* - Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:40 2011 - Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER: -*/ - -module FIFO ( p_reset , m_clock ); - input p_reset, m_clock; - -endmodule -/* - Produced by NSL Core(version=20110302), IP ARCH, Inc. Thu Jun 30 20:35:40 2011 - Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp -*/ diff --git a/VGADisplay/Verilog/vga_gen.v b/VGADisplay/Verilog/vga_gen.v index 5fc4aa6..1628443 100644 --- a/VGADisplay/Verilog/vga_gen.v +++ b/VGADisplay/Verilog/vga_gen.v @@ -1,9 +1,10 @@ /* - Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Jul 23 20:50:38 2011 + Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 25 23:44:36 2011 Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER: */ -module vga_gen ( m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , outled ); +module vga_gen ( i_clk50M , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , i_we1 , i_wrdata1 , i_we2 , i_wrdata2 , i_fifo1_rst , i_fifo2_rst , outled ); + input i_clk50M; input m_clock; input p_reset; output o_vsync; @@ -11,7 +12,15 @@ module vga_gen ( m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_v output [3:0] o_vga_r; output [3:0] o_vga_g; output [3:0] o_vga_b; + input i_we1; + input [7:0] i_wrdata1; + input i_we2; + input [7:0] i_wrdata2; + input i_fifo1_rst; + input i_fifo2_rst; output outled; + wire fi_fifo1_read; + wire fi_fifo2_read; reg r_vsync; reg r_hsync; reg [9:0] r_vcnt; @@ -20,6 +29,21 @@ module vga_gen ( m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_v reg testled; reg [2:0] r_outcnt; reg [6:0] r_outclr; + wire _u_FIFO_p_reset; + wire _u_FIFO_m_clock; + wire _u_FIFO_i_we1; + wire [7:0] _u_FIFO_i_wdata1; + wire _u_FIFO_i_we2; + wire [7:0] _u_FIFO_i_wdata2; + wire [7:0] _u_FIFO_o_rddata1; + wire [7:0] _u_FIFO_o_rddata2; + wire _u_FIFO_i_clock; + wire _u_FIFO_i_re1; + wire _u_FIFO_i_re2; + wire _u_FIFO_i_fifo1_rst; + wire _u_FIFO_i_fifo2_rst; + wire _u_FIFO_o_rdack1; + wire _u_FIFO_o_rdack2; wire _net_0; wire _net_1; wire _net_2; @@ -58,7 +82,20 @@ module vga_gen ( m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_v wire _net_35; wire _net_36; wire _net_37; +vga_ram u_FIFO (.o_rdack2(_u_FIFO_o_rdack2), .o_rdack1(_u_FIFO_o_rdack1), .i_fifo2_rst(_u_FIFO_i_fifo2_rst), .i_fifo1_rst(_u_FIFO_i_fifo1_rst), .i_re2(_u_FIFO_i_re2), .i_re1(_u_FIFO_i_re1), .i_clock(_u_FIFO_i_clock), .o_rddata2(_u_FIFO_o_rddata2), .o_rddata1(_u_FIFO_o_rddata1), .i_wdata2(_u_FIFO_i_wdata2), .i_we2(_u_FIFO_i_we2), .i_wdata1(_u_FIFO_i_wdata1), .i_we1(_u_FIFO_i_we1), .m_clock(_u_FIFO_m_clock), .p_reset(_u_FIFO_p_reset)); + assign fi_fifo1_read = 1'b0; + assign fi_fifo2_read = 1'b0; + assign _u_FIFO_m_clock = i_clk50M; + assign _u_FIFO_i_we1 = i_we1; + assign _u_FIFO_i_wdata1 = i_wrdata1; + assign _u_FIFO_i_we2 = i_we2; + assign _u_FIFO_i_wdata2 = i_wrdata2; + assign _u_FIFO_i_clock = m_clock; + assign _u_FIFO_i_re1 = fi_fifo1_read; + assign _u_FIFO_i_re2 = fi_fifo2_read; + assign _u_FIFO_i_fifo1_rst = i_fifo1_rst; + assign _u_FIFO_i_fifo2_rst = i_fifo2_rst; assign _net_0 = (cnt)==(26'b01011111010111100001000000); assign _net_1 = ~_net_0; assign _net_2 = (r_hcnt) < (10'b1100100000); @@ -178,6 +215,6 @@ else if ((_net_34)|(_net_12)) end endmodule /* - Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Jul 23 20:50:40 2011 + Produced by NSL Core(version=20110302), IP ARCH, Inc. Mon Jul 25 23:44:38 2011 Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp */ diff --git a/VGADisplay/src/vga_gen.nsl b/VGADisplay/src/vga_gen.nsl index 0744bf8..894e02c 100644 --- a/VGADisplay/src/vga_gen.nsl +++ b/VGADisplay/src/vga_gen.nsl @@ -5,7 +5,7 @@ * @version 1.2 */ -#include "vga_ram.nsh" +#include "vga_ram.nsh" // vga ram module #define H_ACT_MAX 10'd640 #define H_FRONTP_MAX 10'd656 @@ -17,12 +17,10 @@ #define V_SYNC_MAX 10'd492 #define V_BACKP_MAX 10'd521 - - #define VCNT_1SEC 26'd25000000 declare vga_gen interface { -// input i_clk50M ; // 50MHz main clock + input i_clk50M ; // 50MHz main clock input m_clock ; input p_reset ; output o_vsync ; @@ -30,18 +28,20 @@ declare vga_gen interface { output o_vga_r[4] ; output o_vga_g[4] ; output o_vga_b[4] ; + + input i_we1 ; + input i_wrdata1[8] ; + input i_we2 ; + input i_wrdata2[8] ; -// input i_color_mode[2] ; + input i_fifo1_rst ; + input i_fifo2_rst ; -// input i_wrdata1[8] ; -// input i_wrdata2[8] ; -// func_in fi_fifo1_write( i_wrdata1 ) ; -// func_in fi_fifo2_write( i_wrdata2 ) ; output outled ; } module vga_gen { -// func_self fs_fifo1_rst ; -// func_self fs_fifo2_rst ; + func_self fi_fifo1_read() ; + func_self fi_fifo2_read() ; reg r_vsync = 0 ; reg r_hsync = 0 ; @@ -51,8 +51,20 @@ module vga_gen { reg testled = 0 ; reg r_outcnt[3] = 0 ; reg r_outclr[7] = 0 ; + + vga_ram u_FIFO ; { + /* FIFO assign */ + u_FIFO.m_clock = i_clk50M ; + u_FIFO.i_we1 = i_we1 ; + u_FIFO.i_wdata1 = i_wrdata1 ; + u_FIFO.i_we2 = i_we2 ; + u_FIFO.i_wdata2 = i_wrdata2 ; + u_FIFO.i_fifo1_rst = i_fifo1_rst ; + u_FIFO.i_fifo2_rst = i_fifo2_rst ; + u_FIFO.i_clock = m_clock ; + /* LED test */ outled = testled ; o_vsync = r_vsync ; @@ -79,14 +91,15 @@ module vga_gen { } if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) ) { + + /* ƒJƒ‰[ƒo[ì¬ */ if( r_outcnt < 3'd4 ) { r_outcnt++ ; } else { r_outcnt := 0 ; r_outclr++ ; } - - /* ƒJƒ‰[ƒo[ì¬ */ + if( ~r_outclr[4]) o_vga_b = ~r_outclr[3:0] ; else o_vga_b = 0 ; @@ -99,6 +112,7 @@ module vga_gen { } else { any { r_hcnt == H_ACT_MAX : { + /* VGA@null@ */ o_vga_r = 0 ; o_vga_g = 0 ; o_vga_b = 0 ; @@ -127,4 +141,12 @@ module vga_gen { } } + func fi_fifo1_read { + u_FIFO.i_re1 = 1 ; + } + + func fi_fifo2_read { + u_FIFO.i_re2 = 1 ; + } + } //module end \ No newline at end of file diff --git a/VGADisplay/src/vga_ram.nsh b/VGADisplay/src/vga_ram.nsh index e1a4856..8460232 100644 --- a/VGADisplay/src/vga_ram.nsh +++ b/VGADisplay/src/vga_ram.nsh @@ -3,13 +3,13 @@ declare vga_ram interface { input m_clock ; input i_we1 ; - input i_wdata1[32] ; + input i_wdata1[8] ; input i_we2 ; - input i_wdata2[32] ; + input i_wdata2[8] ; - output o_rddata1[32] ; - output o_rddata2[32] ; + output o_rddata1[8] ; + output o_rddata2[8] ; input i_clock ; diff --git a/VGADisplay/src/vga_ram.v b/VGADisplay/src/vga_ram.v index 893c78c..a7d2ca6 100644 --- a/VGADisplay/src/vga_ram.v +++ b/VGADisplay/src/vga_ram.v @@ -8,18 +8,15 @@ module vga_ram ( input p_reset ; input m_clock ; - input i_clock ; input i_we1 ; - input [31:0] i_wdata1 ; - + input [7:0] i_wdata1 ; input i_we2 ; - input [31:0] i_wdata2 ; + input [7:0] i_wdata2 ; - output [31:0] o_rddata1 ; - - output [31:0] o_rddata2 ; + output [23:0] o_rddata1 ; + output [23:0] o_rddata2 ; input i_re1 ; input i_re2 ; @@ -33,39 +30,38 @@ module vga_ram ( reg r_hld_re1 = 0 ; reg r_hld_re2 = 0 ; - reg [4:0] r_wradrs1 = 0 ; - reg [4:0] r_wradrs2 = 0 ; - - reg [4:0] r_rdadrs1 = 0 ; - reg [4:0] r_rdadrs2 = 0 ; + reg [7:0] r_wradrs1 = 0 ; + reg [7:0] r_wradrs2 = 0 ; + reg [7:0] r_rdadrs1 = 0 ; + reg [7:0] r_rdadrs2 = 0 ; - (* remstyle = "no_rw_check" *) reg [31:0] mem1[31:0] ; - (* remstyle = "no_rw_check" *) reg [31:0] mem2[31:0] ; + (* remstyle = "no_rw_check" *) reg [7:0] mem1[255:0] ; + (* remstyle = "no_rw_check" *) reg [7:0] mem2[255:0] ; assign o_rdack1 = r_hld_re1 ; assign o_rdack2 = r_hld_re2 ; // memory write command always @ ( posedge i_clock ) begin - if( we1 ) begin + if( i_we1 ) begin mem1[r_wradrs1] <= i_wdata1 ; - r_wradrs1++ ; + r_wradrs1 = r_wradrs1 + 1 ; end end always @ ( posedge i_clock ) begin - if( we2 ) begin - mem1[r_wradrs2] <= i_wdata2 ; - r_wradrs2++ ; + if( i_we2 ) begin + mem2[r_wradrs2] <= i_wdata2 ; + r_wradrs2 = r_wradrs2 + 1 ; end end always @ ( posedge m_clock ) begin - if( i_re1 ) r_rdadrs1++ ; + if( i_re1 ) r_rdadrs1 = r_rdadrs1 + 3'd3 ; end always @ ( posedge m_clock ) begin - if( i_re2 ) r_rdadrs2++ ; + if( i_re2 ) r_rdadrs2 = r_rdadrs2 + 3'd3 ; end always @ ( posedge m_clock ) begin @@ -73,19 +69,26 @@ module vga_ram ( r_hld_re2 = i_re2 ; end - assign q = mem1[r_rdadrs1] ; - assign q = mem2[r_rdadrs2] ; + assign o_rddata1 = { + mem1[r_rdadrs1+8'd2], + mem1[r_rdadrs1+8'd1], + mem1[r_rdadrs1] + } ; + assign o_rddata2 = { + mem2[r_rdadrs2+8'd2], + mem2[r_rdadrs2+8'd1], + mem2[r_rdadrs2] + } ; always @ ( posedge i_clock ) begin if( i_fifo1_rst ) begin - r_wradrs1 = 5'd0 ; - r_wradrs2 = 5'd0 ; + r_wradrs1 = 8'd0 ; + r_rdadrs1 = 8'd0 ; end if( i_fifo2_rst ) begin - r_rdadrs1 = 5'd0 ; - r_rdadrs2 = 5'd0 ; + r_wradrs2 = 8'd0 ; + r_rdadrs2 = 8'd0 ; end - end - + end endmodule \ No newline at end of file -- 2.11.0