From f217791ee27bdd10817109391243ffac5564daad Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 28 Aug 2013 12:06:31 -0700 Subject: [PATCH] i965/gen7: Use the base_level field of the sampler to handle GL's BASE_LEVEL. This avoids the need to get the inter- and intra-tile offset and adjust our miptree info based on them. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/gen7_sampler_state.c | 19 +++++++++---------- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 +++----------- 2 files changed, 12 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_sampler_state.c b/src/mesa/drivers/dri/i965/gen7_sampler_state.c index 193b5b12752..61625022d3d 100644 --- a/src/mesa/drivers/dri/i965/gen7_sampler_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sampler_state.c @@ -25,6 +25,7 @@ #include "brw_state.h" #include "brw_defines.h" #include "intel_batchbuffer.h" +#include "intel_mipmap_tree.h" #include "main/macros.h" #include "main/samplerobj.h" @@ -40,6 +41,8 @@ gen7_update_sampler_state(struct brw_context *brw, int unit, int ss_index, struct gl_context *ctx = &brw->ctx; struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *texObj = texUnit->_Current; + struct intel_texture_image *intel_image = + intel_texture_image(texObj->Image[0][texObj->BaseLevel]); struct gl_sampler_object *gl_sampler = _mesa_get_samplerobj(ctx, unit); bool using_nearest = false; @@ -150,17 +153,13 @@ gen7_update_sampler_state(struct brw_context *brw, int unit, int ss_index, sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ - /* Set BaseMipLevel, MaxLOD, MinLOD: - * - * XXX: I don't think that using firstLevel, lastLevel works, - * because we always setup the surface state as if firstLevel == - * level zero. Probably have to subtract firstLevel from each of - * these: - */ - sampler->ss0.base_level = U_FIXED(0, 1); + int baselevel = texObj->BaseLevel - intel_image->mt->first_level; + sampler->ss0.base_level = U_FIXED(baselevel, 1); - sampler->ss1.max_lod = U_FIXED(CLAMP(gl_sampler->MaxLod, 0, 13), 8); - sampler->ss1.min_lod = U_FIXED(CLAMP(gl_sampler->MinLod, 0, 13), 8); + sampler->ss1.max_lod = U_FIXED(CLAMP(baselevel + + gl_sampler->MaxLod, 0, 13), 8); + sampler->ss1.min_lod = U_FIXED(CLAMP(baselevel + + gl_sampler->MinLod, 0, 13), 8); /* The sampler can handle non-normalized texture rectangle coordinates * natively diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 91f854bd078..b68e2c2d7af 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -284,8 +284,8 @@ gen7_update_texture_surface(struct gl_context *ctx, struct intel_texture_object *intelObj = intel_texture_object(tObj); struct intel_mipmap_tree *mt = intelObj->mt; struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; + struct intel_texture_image *intel_image = intel_texture_image(firstImage); struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); - uint32_t tile_x, tile_y; if (tObj->Target == GL_TEXTURE_BUFFER) { gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); @@ -318,8 +318,6 @@ gen7_update_texture_surface(struct gl_context *ctx, surf[0] |= GEN7_SURFACE_ARYSPC_LOD0; surf[1] = mt->region->bo->offset + mt->offset; /* reloc */ - surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0, - &tile_x, &tile_y); surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) | SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT); @@ -328,15 +326,9 @@ gen7_update_texture_surface(struct gl_context *ctx, surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout); - assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); - /* Note that the low bits of these fields are missing, so - * there's the possibility of getting in trouble. - */ - surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | - (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | - SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) | + surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) | /* mip count */ - (intelObj->_MaxLevel - tObj->BaseLevel)); + (intelObj->_MaxLevel - intel_image->mt->first_level)); if (brw->is_haswell) { /* Handling GL_ALPHA as a surface format override breaks 1.30+ style -- 2.11.0