From f4e9ce12dd88d33c25019e2053ade587d7b95969 Mon Sep 17 00:00:00 2001 From: James Morse Date: Wed, 30 Nov 2022 17:16:26 +0000 Subject: [PATCH] arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation Convert ID_ISAR5_EL1 to be automatically generated as per DDI0487I.a, no functional changes. Reviewed-by: Mark Brown Signed-off-by: James Morse Link: https://lore.kernel.org/r/20221130171637.718182-28-james.morse@arm.com Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 8 -------- arch/arm64/tools/sysreg | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 0a63c39407f2..04a6e44427a9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -173,7 +173,6 @@ #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) -#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) @@ -689,13 +688,6 @@ #define ID_DFR1_EL1_MTPMU_SHIFT 0 -#define ID_ISAR5_EL1_RDM_SHIFT 24 -#define ID_ISAR5_EL1_CRC32_SHIFT 16 -#define ID_ISAR5_EL1_SHA2_SHIFT 12 -#define ID_ISAR5_EL1_SHA1_SHIFT 8 -#define ID_ISAR5_EL1_AES_SHIFT 4 -#define ID_ISAR5_EL1_SEVL_SHIFT 0 - #define ID_ISAR6_EL1_I8MM_SHIFT 24 #define ID_ISAR6_EL1_BF16_SHIFT 20 #define ID_ISAR6_EL1_SPECRES_SHIFT 16 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ed88cc1ae2a8..43e765a2c68f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -421,6 +421,40 @@ Enum 3:0 Unpriv EndEnum EndSysreg +Sysreg ID_ISAR5_EL1 3 0 0 2 5 +Res0 63:32 +Enum 31:28 VCMA + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 27:24 RDM + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 23:20 +Enum 19:16 CRC32 + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 SHA2 + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 SHA1 + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 7:4 AES + 0b0000 NI + 0b0001 IMP + 0b0010 VMULL +EndEnum +Enum 3:0 SEVL + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_MMFR4_EL1 3 0 0 2 6 Res0 63:32 Enum 31:28 EVT -- 2.11.0