From f52efce72d9a41c4cd18fe2ccba41b7cf9ed1b00 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Fri, 15 Aug 2014 10:47:12 +0000 Subject: [PATCH] ARM: implement MRS/MSR (banked reg) system instructions. These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215700 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrFormats.td | 10 + lib/Target/ARM/ARMInstrInfo.td | 49 ++++- lib/Target/ARM/ARMInstrThumb2.td | 36 ++++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 88 +++++++++ lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 25 +++ lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 36 ++++ lib/Target/ARM/InstPrinter/ARMInstPrinter.h | 1 + test/MC/ARM/move-banked-regs.s | 220 +++++++++++++++++++++ test/MC/Disassembler/ARM/move-banked-regs-arm.txt | 150 ++++++++++++++ .../MC/Disassembler/ARM/move-banked-regs-thumb.txt | 153 ++++++++++++++ 10 files changed, 764 insertions(+), 4 deletions(-) create mode 100644 test/MC/ARM/move-banked-regs.s create mode 100644 test/MC/Disassembler/ARM/move-banked-regs-arm.txt create mode 100644 test/MC/Disassembler/ARM/move-banked-regs-thumb.txt diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 59e9260b81e..7d27cf3fcdc 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -203,6 +203,16 @@ def msr_mask : Operand { let ParserMatchClass = MSRMaskOperand; } +def BankedRegOperand : AsmOperandClass { + let Name = "BankedReg"; + let ParserMethod = "parseBankedRegOperand"; +} +def banked_reg : Operand { + let PrintMethod = "printBankedRegOperand"; + let DecoderMethod = "DecodeBankedReg"; + let ParserMatchClass = BankedRegOperand; +} + // Shift Right Immediate - A shift right immediate is encoded differently from // other shift immediates. The imm6 field is encoded like so: // diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index f6cf69a2fbb..e7640f0e98f 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -241,6 +241,9 @@ def HasDB : Predicate<"Subtarget->hasDataBarrier()">, def HasMP : Predicate<"Subtarget->hasMPExtension()">, AssemblerPredicate<"FeatureMP", "mp-extensions">; +def HasVirtualization: Predicate<"false">, + AssemblerPredicate<"FeatureVirtualization", + "virtualization-extensions">; def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, AssemblerPredicate<"FeatureTrustZone", "TrustZone">; @@ -5066,12 +5069,31 @@ def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, let Unpredictable{11-0} = 0b110100001111; } +// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a +// separate encoding (distinguished by bit 5. +def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), + NoItinerary, "mrs", "\t$Rd, $banked", []>, + Requires<[IsARM, HasVirtualization]> { + bits<6> banked; + bits<4> Rd; + + let Inst{23} = 0; + let Inst{22} = banked{5}; // R bit + let Inst{21-20} = 0b10; + let Inst{19-16} = banked{3-0}; + let Inst{15-12} = Rd; + let Inst{11-9} = 0b001; + let Inst{8} = banked{4}; + let Inst{7-0} = 0b00000000; +} + // Move from ARM core register to Special Register // -// No need to have both system and application versions, the encodings are the -// same and the assembly parser has no way to distinguish between them. The mask -// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains -// the mask with the fields to be accessed in the special register. +// No need to have both system and application versions of MSR (immediate) or +// MSR (register), the encodings are the same and the assembly parser has no way +// to distinguish between them. The mask operand contains the special register +// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be +// accessed in the special register. def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, "msr", "\t$mask, $Rn", []> { bits<5> mask; @@ -5099,6 +5121,25 @@ def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, let Inst{11-0} = a; } +// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a +// separate encoding (distinguished by bit 5. +def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), + NoItinerary, "msr", "\t$banked, $Rn", []>, + Requires<[IsARM, HasVirtualization]> { + bits<6> banked; + bits<4> Rn; + + let Inst{23} = 0; + let Inst{22} = banked{5}; // R bit + let Inst{21-20} = 0b10; + let Inst{19-16} = banked{3-0}; + let Inst{15-12} = 0b1111; + let Inst{11-9} = 0b001; + let Inst{8} = banked{4}; + let Inst{7-4} = 0b0000; + let Inst{3-0} = Rn; +} + // Dynamic stack allocation yields a _chkstk for Windows targets. These calls // are needed to probe the stack when allocating more than // 4k bytes in one go. Touching the stack at 4K increments is necessary to diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 46dbd8c95ed..e6d17e88755 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3991,6 +3991,23 @@ def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", let Inst{7-0} = 0b00000000; } +def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked), + NoItinerary, "mrs", "\t$Rd, $banked", []>, + Requires<[IsThumb, HasVirtualization]> { + bits<6> banked; + bits<4> Rd; + + let Inst{31-21} = 0b11110011111; + let Inst{20} = banked{5}; // R bit + let Inst{19-16} = banked{3-0}; + let Inst{15-12} = 0b1000; + let Inst{11-8} = Rd; + let Inst{7-5} = 0b001; + let Inst{4} = banked{4}; + let Inst{3-0} = 0b0000; +} + + // M class MRS. // // This MRS has a mask field in bits 7-0 and can take more values than @@ -4028,6 +4045,25 @@ def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn), let Inst{7-0} = 0; } +// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a +// separate encoding (distinguished by bit 5. +def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn), + NoItinerary, "msr", "\t$banked, $Rn", []>, + Requires<[IsThumb, HasVirtualization]> { + bits<6> banked; + bits<4> Rn; + + let Inst{31-21} = 0b11110011100; + let Inst{20} = banked{5}; // R bit + let Inst{19-16} = Rn; + let Inst{15-12} = 0b1000; + let Inst{11-8} = banked{3-0}; + let Inst{7-5} = 0b001; + let Inst{4} = banked{4}; + let Inst{3-0} = 0b0000; +} + + // M class MSR. // // Move from ARM core register to Special Register diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index da6b700e607..ba46c937d80 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -290,6 +290,7 @@ class ARMAsmParser : public MCTargetAsmParser { OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); OperandMatchResultTy parseMSRMaskOperand(OperandVector &); + OperandMatchResultTy parseBankedRegOperand(OperandVector &); OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, int High); OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { @@ -383,6 +384,7 @@ class ARMOperand : public MCParsedAsmOperand { k_Memory, k_PostIndexRegister, k_MSRMask, + k_BankedReg, k_ProcIFlags, k_VectorIndex, k_Register, @@ -435,6 +437,10 @@ class ARMOperand : public MCParsedAsmOperand { unsigned Val; }; + struct BankedRegOp { + unsigned Val; + }; + struct TokOp { const char *Data; unsigned Length; @@ -517,6 +523,7 @@ class ARMOperand : public MCParsedAsmOperand { struct ITMaskOp ITMask; struct IFlagsOp IFlags; struct MMaskOp MMask; + struct BankedRegOp BankedReg; struct TokOp Tok; struct RegOp Reg; struct VectorListOp VectorList; @@ -585,6 +592,9 @@ public: case k_MSRMask: MMask = o.MMask; break; + case k_BankedReg: + BankedReg = o.BankedReg; + break; case k_ProcIFlags: IFlags = o.IFlags; break; @@ -679,6 +689,11 @@ public: return MMask.Val; } + unsigned getBankedReg() const { + assert(Kind == k_BankedReg && "Invalid access!"); + return BankedReg.Val; + } + bool isCoprocNum() const { return Kind == k_CoprocNum; } bool isCoprocReg() const { return Kind == k_CoprocReg; } bool isCoprocOption() const { return Kind == k_CoprocOption; } @@ -1384,6 +1399,7 @@ public: } bool isMSRMask() const { return Kind == k_MSRMask; } + bool isBankedReg() const { return Kind == k_BankedReg; } bool isProcIFlags() const { return Kind == k_ProcIFlags; } // NEON operands. @@ -2334,6 +2350,11 @@ public: Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); } + void addBankedRegOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg()))); + } + void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); @@ -2736,6 +2757,14 @@ public: Op->EndLoc = S; return Op; } + + static std::unique_ptr CreateBankedReg(unsigned Reg, SMLoc S) { + auto Op = make_unique(k_BankedReg); + Op->BankedReg.Val = Reg; + Op->StartLoc = S; + Op->EndLoc = S; + return Op; + } }; } // end anonymous namespace. @@ -2769,6 +2798,9 @@ void ARMOperand::print(raw_ostream &OS) const { case k_MSRMask: OS << ""; break; + case k_BankedReg: + OS << ""; + break; case k_Immediate: getImm()->print(OS); break; @@ -4002,6 +4034,62 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { return MatchOperand_Success; } +/// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for +/// use in the MRS/MSR instructions added to support virtualization. +ARMAsmParser::OperandMatchResultTy +ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { + SMLoc S = Parser.getTok().getLoc(); + const AsmToken &Tok = Parser.getTok(); + if (!Tok.is(AsmToken::Identifier)) + return MatchOperand_NoMatch; + StringRef RegName = Tok.getString(); + + // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM + // and bit 5 is R. + unsigned Encoding = StringSwitch(RegName.lower()) + .Case("r8_usr", 0x00) + .Case("r9_usr", 0x01) + .Case("r10_usr", 0x02) + .Case("r11_usr", 0x03) + .Case("r12_usr", 0x04) + .Case("sp_usr", 0x05) + .Case("lr_usr", 0x06) + .Case("r8_fiq", 0x08) + .Case("r9_fiq", 0x09) + .Case("r10_fiq", 0x0a) + .Case("r11_fiq", 0x0b) + .Case("r12_fiq", 0x0c) + .Case("sp_fiq", 0x0d) + .Case("lr_fiq", 0x0e) + .Case("lr_irq", 0x10) + .Case("sp_irq", 0x11) + .Case("lr_svc", 0x12) + .Case("sp_svc", 0x13) + .Case("lr_abt", 0x14) + .Case("sp_abt", 0x15) + .Case("lr_und", 0x16) + .Case("sp_und", 0x17) + .Case("lr_mon", 0x1c) + .Case("sp_mon", 0x1d) + .Case("elr_hyp", 0x1e) + .Case("sp_hyp", 0x1f) + .Case("spsr_fiq", 0x2e) + .Case("spsr_irq", 0x30) + .Case("spsr_svc", 0x32) + .Case("spsr_abt", 0x34) + .Case("spsr_und", 0x36) + .Case("spsr_mon", 0x3c) + .Case("spsr_hyp", 0x3e) + .Default(~0U); + + if (Encoding == ~0U) + return MatchOperand_NoMatch; + + Parser.Lex(); // Eat identifier token. + Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); + return MatchOperand_Success; +} + ARMAsmParser::OperandMatchResultTy ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, int High) { diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 48bcc9b2dcd..0940e2a2407 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -281,6 +281,8 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, @@ -4025,6 +4027,29 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, return MCDisassembler::Success; } +static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + + unsigned R = fieldFromInstruction(Val, 5, 1); + unsigned SysM = fieldFromInstruction(Val, 0, 5); + + // The table of encodings for these banked registers comes from B9.2.3 of the + // ARM ARM. There are patterns, but nothing regular enough to make this logic + // neater. So by fiat, these values are UNPREDICTABLE: + if (!R) { + if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || + SysM == 0x1a || SysM == 0x1b) + return MCDisassembler::SoftFail; + } else { + if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && + SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) + return MCDisassembler::SoftFail; + } + + Inst.addOperand(MCOperand::CreateImm(Val)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 228fb5756ca..5782ae39cf0 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -882,6 +882,42 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, } } +void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + uint32_t Banked = MI->getOperand(OpNum).getImm(); + uint32_t R = (Banked & 0x20) >> 5; + uint32_t SysM = Banked & 0x1f; + + // Nothing much we can do about this, the encodings are specified in B9.2.3 of + // the ARM ARM v7C, and are all over the shop. + if (R) { + O << "SPSR_"; + + switch(SysM) { + case 0x0e: O << "fiq"; return; + case 0x10: O << "irq"; return; + case 0x12: O << "svc"; return; + case 0x14: O << "abt"; return; + case 0x16: O << "und"; return; + case 0x1c: O << "mon"; return; + case 0x1e: O << "hyp"; return; + default: llvm_unreachable("Invalid banked SPSR register"); + } + } + + assert(!R && "should have dealt with SPSR regs"); + const char *RegNames[] = { + "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", "", + "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq", "", + "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt", "sp_abt", "lr_und", "sp_und", + "", "", "", "", "lr_mon", "sp_mon", "elr_hyp", "sp_hyp" + }; + const char *Name = RegNames[SysM]; + assert(Name[0] && "invalid banked register operand"); + + O << Name; +} + void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.h b/lib/Target/ARM/InstPrinter/ARMInstPrinter.h index 45b92adae92..451eaa51ef2 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.h +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.h @@ -117,6 +117,7 @@ public: void printCPSIMod(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printCPSIFlag(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printBankedRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); diff --git a/test/MC/ARM/move-banked-regs.s b/test/MC/ARM/move-banked-regs.s new file mode 100644 index 00000000000..3fac84694b9 --- /dev/null +++ b/test/MC/ARM/move-banked-regs.s @@ -0,0 +1,220 @@ +@ RUN: llvm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM +@ RUN: llvm-mc -triple thumbv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-THUMB + + mrs r2, r8_usr + mrs r3, r9_usr + mrs r5, r10_usr + mrs r7, r11_usr + mrs r11, r12_usr + mrs r1, sp_usr + mrs r2, lr_usr +@ CHECK-ARM: mrs r2, r8_usr @ encoding: [0x00,0x22,0x20,0xe1] +@ CHECK-ARM: mrs r3, r9_usr @ encoding: [0x00,0x32,0x21,0xe1] +@ CHECK-ARM: mrs r5, r10_usr @ encoding: [0x00,0x52,0x22,0xe1] +@ CHECK-ARM: mrs r7, r11_usr @ encoding: [0x00,0x72,0x23,0xe1] +@ CHECK-ARM: mrs r11, r12_usr @ encoding: [0x00,0xb2,0x24,0xe1] +@ CHECK-ARM: mrs r1, sp_usr @ encoding: [0x00,0x12,0x25,0xe1] +@ CHECK-ARM: mrs r2, lr_usr @ encoding: [0x00,0x22,0x26,0xe1] +@ CHECK-THUMB: mrs r2, r8_usr @ encoding: [0xe0,0xf3,0x20,0x82] +@ CHECK-THUMB: mrs r3, r9_usr @ encoding: [0xe1,0xf3,0x20,0x83] +@ CHECK-THUMB: mrs r5, r10_usr @ encoding: [0xe2,0xf3,0x20,0x85] +@ CHECK-THUMB: mrs r7, r11_usr @ encoding: [0xe3,0xf3,0x20,0x87] +@ CHECK-THUMB: mrs r11, r12_usr @ encoding: [0xe4,0xf3,0x20,0x8b] +@ CHECK-THUMB: mrs r1, sp_usr @ encoding: [0xe5,0xf3,0x20,0x81] +@ CHECK-THUMB: mrs r2, lr_usr @ encoding: [0xe6,0xf3,0x20,0x82] + + mrs r2, r8_fiq + mrs r3, r9_fiq + mrs r5, r10_fiq + mrs r7, r11_fiq + mrs r11, r12_fiq + mrs r1, sp_fiq + mrs r2, lr_fiq + mrs r3, spsr_fiq +@ CHECK-ARM: mrs r2, r8_fiq @ encoding: [0x00,0x22,0x28,0xe1] +@ CHECK-ARM: mrs r3, r9_fiq @ encoding: [0x00,0x32,0x29,0xe1] +@ CHECK-ARM: mrs r5, r10_fiq @ encoding: [0x00,0x52,0x2a,0xe1] +@ CHECK-ARM: mrs r7, r11_fiq @ encoding: [0x00,0x72,0x2b,0xe1] +@ CHECK-ARM: mrs r11, r12_fiq @ encoding: [0x00,0xb2,0x2c,0xe1] +@ CHECK-ARM: mrs r1, sp_fiq @ encoding: [0x00,0x12,0x2d,0xe1] +@ CHECK-ARM: mrs r2, lr_fiq @ encoding: [0x00,0x22,0x2e,0xe1] +@ CHECK-ARM: mrs r3, SPSR_fiq @ encoding: [0x00,0x32,0x6e,0xe1] +@ CHECK-THUMB: mrs r2, r8_fiq @ encoding: [0xe8,0xf3,0x20,0x82] +@ CHECK-THUMB: mrs r3, r9_fiq @ encoding: [0xe9,0xf3,0x20,0x83] +@ CHECK-THUMB: mrs r5, r10_fiq @ encoding: [0xea,0xf3,0x20,0x85] +@ CHECK-THUMB: mrs r7, r11_fiq @ encoding: [0xeb,0xf3,0x20,0x87] +@ CHECK-THUMB: mrs r11, r12_fiq @ encoding: [0xec,0xf3,0x20,0x8b] +@ CHECK-THUMB: mrs r1, sp_fiq @ encoding: [0xed,0xf3,0x20,0x81] +@ CHECK-THUMB: mrs r2, lr_fiq @ encoding: [0xee,0xf3,0x20,0x82] +@ CHECK-THUMB: mrs r3, SPSR_fiq @ encoding: [0xfe,0xf3,0x20,0x83] + + mrs r4, lr_irq + mrs r9, sp_irq + mrs r1, spsr_irq +@ CHECK-ARM: mrs r4, lr_irq @ encoding: [0x00,0x43,0x20,0xe1] +@ CHECK-ARM: mrs r9, sp_irq @ encoding: [0x00,0x93,0x21,0xe1] +@ CHECK-ARM: mrs r1, SPSR_irq @ encoding: [0x00,0x13,0x60,0xe1] +@ CHECK-THUMB: mrs r4, lr_irq @ encoding: [0xe0,0xf3,0x30,0x84] +@ CHECK-THUMB: mrs r9, sp_irq @ encoding: [0xe1,0xf3,0x30,0x89] +@ CHECK-THUMB: mrs r1, SPSR_irq @ encoding: [0xf0,0xf3,0x30,0x81] + + mrs r1, lr_svc + mrs r3, sp_svc + mrs r5, spsr_svc +@ CHECK-ARM: mrs r1, lr_svc @ encoding: [0x00,0x13,0x22,0xe1] +@ CHECK-ARM: mrs r3, sp_svc @ encoding: [0x00,0x33,0x23,0xe1] +@ CHECK-ARM: mrs r5, SPSR_svc @ encoding: [0x00,0x53,0x62,0xe1] +@ CHECK-THUMB: mrs r1, lr_svc @ encoding: [0xe2,0xf3,0x30,0x81] +@ CHECK-THUMB: mrs r3, sp_svc @ encoding: [0xe3,0xf3,0x30,0x83] +@ CHECK-THUMB: mrs r5, SPSR_svc @ encoding: [0xf2,0xf3,0x30,0x85] + + mrs r5, lr_abt + mrs r7, sp_abt + mrs r9, spsr_abt +@ CHECK-ARM: mrs r5, lr_abt @ encoding: [0x00,0x53,0x24,0xe1] +@ CHECK-ARM: mrs r7, sp_abt @ encoding: [0x00,0x73,0x25,0xe1] +@ CHECK-ARM: mrs r9, SPSR_abt @ encoding: [0x00,0x93,0x64,0xe1] +@ CHECK-THUMB: mrs r5, lr_abt @ encoding: [0xe4,0xf3,0x30,0x85] +@ CHECK-THUMB: mrs r7, sp_abt @ encoding: [0xe5,0xf3,0x30,0x87] +@ CHECK-THUMB: mrs r9, SPSR_abt @ encoding: [0xf4,0xf3,0x30,0x89] + + mrs r9, lr_und + mrs r11, sp_und + mrs r12, spsr_und +@ CHECK-ARM: mrs r9, lr_und @ encoding: [0x00,0x93,0x26,0xe1] +@ CHECK-ARM: mrs r11, sp_und @ encoding: [0x00,0xb3,0x27,0xe1] +@ CHECK-ARM: mrs r12, SPSR_und @ encoding: [0x00,0xc3,0x66,0xe1] +@ CHECK-THUMB: mrs r9, lr_und @ encoding: [0xe6,0xf3,0x30,0x89] +@ CHECK-THUMB: mrs r11, sp_und @ encoding: [0xe7,0xf3,0x30,0x8b] +@ CHECK-THUMB: mrs r12, SPSR_und @ encoding: [0xf6,0xf3,0x30,0x8c] + + + mrs r2, lr_mon + mrs r4, sp_mon + mrs r6, spsr_mon +@ CHECK-ARM: mrs r2, lr_mon @ encoding: [0x00,0x23,0x2c,0xe1] +@ CHECK-ARM: mrs r4, sp_mon @ encoding: [0x00,0x43,0x2d,0xe1] +@ CHECK-ARM: mrs r6, SPSR_mon @ encoding: [0x00,0x63,0x6c,0xe1] +@ CHECK-THUMB: mrs r2, lr_mon @ encoding: [0xec,0xf3,0x30,0x82] +@ CHECK-THUMB: mrs r4, sp_mon @ encoding: [0xed,0xf3,0x30,0x84] +@ CHECK-THUMB: mrs r6, SPSR_mon @ encoding: [0xfc,0xf3,0x30,0x86] + + + mrs r6, elr_hyp + mrs r8, sp_hyp + mrs r10, spsr_hyp +@ CHECK-ARM: mrs r6, elr_hyp @ encoding: [0x00,0x63,0x2e,0xe1] +@ CHECK-ARM: mrs r8, sp_hyp @ encoding: [0x00,0x83,0x2f,0xe1] +@ CHECK-ARM: mrs r10, SPSR_hyp @ encoding: [0x00,0xa3,0x6e,0xe1] +@ CHECK-THUMB: mrs r6, elr_hyp @ encoding: [0xee,0xf3,0x30,0x86] +@ CHECK-THUMB: mrs r8, sp_hyp @ encoding: [0xef,0xf3,0x30,0x88] +@ CHECK-THUMB: mrs r10, SPSR_hyp @ encoding: [0xfe,0xf3,0x30,0x8a] + + + msr r8_usr, r2 + msr r9_usr, r3 + msr r10_usr, r5 + msr r11_usr, r7 + msr r12_usr, r11 + msr sp_usr, r1 + msr lr_usr, r2 +@ CHECK-ARM: msr r8_usr, r2 @ encoding: [0x02,0xf2,0x20,0xe1] +@ CHECK-ARM: msr r9_usr, r3 @ encoding: [0x03,0xf2,0x21,0xe1] +@ CHECK-ARM: msr r10_usr, r5 @ encoding: [0x05,0xf2,0x22,0xe1] +@ CHECK-ARM: msr r11_usr, r7 @ encoding: [0x07,0xf2,0x23,0xe1] +@ CHECK-ARM: msr r12_usr, r11 @ encoding: [0x0b,0xf2,0x24,0xe1] +@ CHECK-ARM: msr sp_usr, r1 @ encoding: [0x01,0xf2,0x25,0xe1] +@ CHECK-ARM: msr lr_usr, r2 @ encoding: [0x02,0xf2,0x26,0xe1] +@ CHECK-THUMB: msr r8_usr, r2 @ encoding: [0x82,0xf3,0x20,0x80] +@ CHECK-THUMB: msr r9_usr, r3 @ encoding: [0x83,0xf3,0x20,0x81] +@ CHECK-THUMB: msr r10_usr, r5 @ encoding: [0x85,0xf3,0x20,0x82] +@ CHECK-THUMB: msr r11_usr, r7 @ encoding: [0x87,0xf3,0x20,0x83] +@ CHECK-THUMB: msr r12_usr, r11 @ encoding: [0x8b,0xf3,0x20,0x84] +@ CHECK-THUMB: msr sp_usr, r1 @ encoding: [0x81,0xf3,0x20,0x85] +@ CHECK-THUMB: msr lr_usr, r2 @ encoding: [0x82,0xf3,0x20,0x86] + + msr r8_fiq, r2 + msr r9_fiq, r3 + msr r10_fiq, r5 + msr r11_fiq, r7 + msr r12_fiq, r11 + msr sp_fiq, r1 + msr lr_fiq, r2 + msr spsr_fiq, r3 +@ CHECK-ARM: msr r8_fiq, r2 @ encoding: [0x02,0xf2,0x28,0xe1] +@ CHECK-ARM: msr r9_fiq, r3 @ encoding: [0x03,0xf2,0x29,0xe1] +@ CHECK-ARM: msr r10_fiq, r5 @ encoding: [0x05,0xf2,0x2a,0xe1] +@ CHECK-ARM: msr r11_fiq, r7 @ encoding: [0x07,0xf2,0x2b,0xe1] +@ CHECK-ARM: msr r12_fiq, r11 @ encoding: [0x0b,0xf2,0x2c,0xe1] +@ CHECK-ARM: msr sp_fiq, r1 @ encoding: [0x01,0xf2,0x2d,0xe1] +@ CHECK-ARM: msr lr_fiq, r2 @ encoding: [0x02,0xf2,0x2e,0xe1] +@ CHECK-ARM: msr SPSR_fiq, r3 @ encoding: [0x03,0xf2,0x6e,0xe1] +@ CHECK-THUMB: msr r8_fiq, r2 @ encoding: [0x82,0xf3,0x20,0x88] +@ CHECK-THUMB: msr r9_fiq, r3 @ encoding: [0x83,0xf3,0x20,0x89] +@ CHECK-THUMB: msr r10_fiq, r5 @ encoding: [0x85,0xf3,0x20,0x8a] +@ CHECK-THUMB: msr r11_fiq, r7 @ encoding: [0x87,0xf3,0x20,0x8b] +@ CHECK-THUMB: msr r12_fiq, r11 @ encoding: [0x8b,0xf3,0x20,0x8c] +@ CHECK-THUMB: msr sp_fiq, r1 @ encoding: [0x81,0xf3,0x20,0x8d] +@ CHECK-THUMB: msr lr_fiq, r2 @ encoding: [0x82,0xf3,0x20,0x8e] +@ CHECK-THUMB: msr SPSR_fiq, r3 @ encoding: [0x93,0xf3,0x20,0x8e] + + msr lr_irq, r4 + msr sp_irq, r9 + msr spsr_irq, r11 +@ CHECK-ARM: msr lr_irq, r4 @ encoding: [0x04,0xf3,0x20,0xe1] +@ CHECK-ARM: msr sp_irq, r9 @ encoding: [0x09,0xf3,0x21,0xe1] +@ CHECK-ARM: msr SPSR_irq, r11 @ encoding: [0x0b,0xf3,0x60,0xe1] +@ CHECK-THUMB: msr lr_irq, r4 @ encoding: [0x84,0xf3,0x30,0x80] +@ CHECK-THUMB: msr sp_irq, r9 @ encoding: [0x89,0xf3,0x30,0x81] +@ CHECK-THUMB: msr SPSR_irq, r11 @ encoding: [0x9b,0xf3,0x30,0x80] + + msr lr_svc, r1 + msr sp_svc, r3 + msr spsr_svc, r5 +@ CHECK-ARM: msr lr_svc, r1 @ encoding: [0x01,0xf3,0x22,0xe1] +@ CHECK-ARM: msr sp_svc, r3 @ encoding: [0x03,0xf3,0x23,0xe1] +@ CHECK-ARM: msr SPSR_svc, r5 @ encoding: [0x05,0xf3,0x62,0xe1] +@ CHECK-THUMB: msr lr_svc, r1 @ encoding: [0x81,0xf3,0x30,0x82] +@ CHECK-THUMB: msr sp_svc, r3 @ encoding: [0x83,0xf3,0x30,0x83] +@ CHECK-THUMB: msr SPSR_svc, r5 @ encoding: [0x95,0xf3,0x30,0x82] + + msr lr_abt, r5 + msr sp_abt, r7 + msr spsr_abt, r9 +@ CHECK-ARM: msr lr_abt, r5 @ encoding: [0x05,0xf3,0x24,0xe1] +@ CHECK-ARM: msr sp_abt, r7 @ encoding: [0x07,0xf3,0x25,0xe1] +@ CHECK-ARM: msr SPSR_abt, r9 @ encoding: [0x09,0xf3,0x64,0xe1] +@ CHECK-THUMB: msr lr_abt, r5 @ encoding: [0x85,0xf3,0x30,0x84] +@ CHECK-THUMB: msr sp_abt, r7 @ encoding: [0x87,0xf3,0x30,0x85] +@ CHECK-THUMB: msr SPSR_abt, r9 @ encoding: [0x99,0xf3,0x30,0x84] + + msr lr_und, r9 + msr sp_und, r11 + msr spsr_und, r12 +@ CHECK-ARM: msr lr_und, r9 @ encoding: [0x09,0xf3,0x26,0xe1] +@ CHECK-ARM: msr sp_und, r11 @ encoding: [0x0b,0xf3,0x27,0xe1] +@ CHECK-ARM: msr SPSR_und, r12 @ encoding: [0x0c,0xf3,0x66,0xe1] +@ CHECK-THUMB: msr lr_und, r9 @ encoding: [0x89,0xf3,0x30,0x86] +@ CHECK-THUMB: msr sp_und, r11 @ encoding: [0x8b,0xf3,0x30,0x87] +@ CHECK-THUMB: msr SPSR_und, r12 @ encoding: [0x9c,0xf3,0x30,0x86] + + + msr lr_mon, r2 + msr sp_mon, r4 + msr spsr_mon, r6 +@ CHECK-ARM: msr lr_mon, r2 @ encoding: [0x02,0xf3,0x2c,0xe1] +@ CHECK-ARM: msr sp_mon, r4 @ encoding: [0x04,0xf3,0x2d,0xe1] +@ CHECK-ARM: msr SPSR_mon, r6 @ encoding: [0x06,0xf3,0x6c,0xe1] +@ CHECK-THUMB: msr lr_mon, r2 @ encoding: [0x82,0xf3,0x30,0x8c] +@ CHECK-THUMB: msr sp_mon, r4 @ encoding: [0x84,0xf3,0x30,0x8d] +@ CHECK-THUMB: msr SPSR_mon, r6 @ encoding: [0x96,0xf3,0x30,0x8c] + + msr elr_hyp, r6 + msr sp_hyp, r8 + msr spsr_hyp, r10 +@ CHECK-ARM: msr elr_hyp, r6 @ encoding: [0x06,0xf3,0x2e,0xe1] +@ CHECK-ARM: msr sp_hyp, r8 @ encoding: [0x08,0xf3,0x2f,0xe1] +@ CHECK-ARM: msr SPSR_hyp, r10 @ encoding: [0x0a,0xf3,0x6e,0xe1] +@ CHECK-THUMB: msr elr_hyp, r6 @ encoding: [0x86,0xf3,0x30,0x8e] +@ CHECK-THUMB: msr sp_hyp, r8 @ encoding: [0x88,0xf3,0x30,0x8f] +@ CHECK-THUMB: msr SPSR_hyp, r10 @ encoding: [0x9a,0xf3,0x30,0x8e] diff --git a/test/MC/Disassembler/ARM/move-banked-regs-arm.txt b/test/MC/Disassembler/ARM/move-banked-regs-arm.txt new file mode 100644 index 00000000000..dd1d463f242 --- /dev/null +++ b/test/MC/Disassembler/ARM/move-banked-regs-arm.txt @@ -0,0 +1,150 @@ +@ RUN: llvm-mc -disassemble -triple armv7 -mcpu=cyclone %s | FileCheck %s + + +[0x00,0x22,0x20,0xe1] +[0x00,0x32,0x21,0xe1] +[0x00,0x52,0x22,0xe1] +[0x00,0x72,0x23,0xe1] +[0x00,0xb2,0x24,0xe1] +[0x00,0x12,0x25,0xe1] +[0x00,0x22,0x26,0xe1] +@ CHECK: mrs r2, r8_usr +@ CHECK: mrs r3, r9_usr +@ CHECK: mrs r5, r10_usr +@ CHECK: mrs r7, r11_usr +@ CHECK: mrs r11, r12_usr +@ CHECK: mrs r1, sp_usr +@ CHECK: mrs r2, lr_usr + +[0x00,0x22,0x28,0xe1] +[0x00,0x32,0x29,0xe1] +[0x00,0x52,0x2a,0xe1] +[0x00,0x72,0x2b,0xe1] +[0x00,0xb2,0x2c,0xe1] +[0x00,0x12,0x2d,0xe1] +[0x00,0x22,0x2e,0xe1] +[0x00,0x32,0x6e,0xe1] +@ CHECK: mrs r2, r8_fiq +@ CHECK: mrs r3, r9_fiq +@ CHECK: mrs r5, r10_fiq +@ CHECK: mrs r7, r11_fiq +@ CHECK: mrs r11, r12_fiq +@ CHECK: mrs r1, sp_fiq +@ CHECK: mrs r2, lr_fiq +@ CHECK: mrs r3, SPSR_fiq + +[0x00,0x43,0x20,0xe1] +[0x00,0x93,0x21,0xe1] +[0x00,0x13,0x60,0xe1] +@ CHECK: mrs r4, lr_irq +@ CHECK: mrs r9, sp_irq +@ CHECK: mrs r1, SPSR_irq + +[0x00,0x13,0x22,0xe1] +[0x00,0x33,0x23,0xe1] +[0x00,0x53,0x62,0xe1] +@ CHECK: mrs r1, lr_svc +@ CHECK: mrs r3, sp_svc +@ CHECK: mrs r5, SPSR_svc + +[0x00,0x53,0x24,0xe1] +[0x00,0x73,0x25,0xe1] +[0x00,0x93,0x64,0xe1] +@ CHECK: mrs r5, lr_abt +@ CHECK: mrs r7, sp_abt +@ CHECK: mrs r9, SPSR_abt + +[0x00,0x93,0x26,0xe1] +[0x00,0xb3,0x27,0xe1] +[0x00,0xc3,0x66,0xe1] +@ CHECK: mrs r9, lr_und +@ CHECK: mrs r11, sp_und +@ CHECK: mrs r12, SPSR_und + +[0x00,0x23,0x2c,0xe1] +[0x00,0x43,0x2d,0xe1] +[0x00,0x63,0x6c,0xe1] +@ CHECK: mrs r2, lr_mon +@ CHECK: mrs r4, sp_mon +@ CHECK: mrs r6, SPSR_mon + +[0x00,0x63,0x2e,0xe1] +[0x00,0x83,0x2f,0xe1] +[0x00,0xa3,0x6e,0xe1] +@ CHECK: mrs r6, elr_hyp +@ CHECK: mrs r8, sp_hyp +@ CHECK: mrs r10, SPSR_hyp + +[0x02,0xf2,0x20,0xe1] +[0x03,0xf2,0x21,0xe1] +[0x05,0xf2,0x22,0xe1] +[0x07,0xf2,0x23,0xe1] +[0x0b,0xf2,0x24,0xe1] +[0x01,0xf2,0x25,0xe1] +[0x02,0xf2,0x26,0xe1] +@ CHECK: msr r8_usr, r2 +@ CHECK: msr r9_usr, r3 +@ CHECK: msr r10_usr, r5 +@ CHECK: msr r11_usr, r7 +@ CHECK: msr r12_usr, r11 +@ CHECK: msr sp_usr, r1 +@ CHECK: msr lr_usr, r2 + +[0x02,0xf2,0x28,0xe1] +[0x03,0xf2,0x29,0xe1] +[0x05,0xf2,0x2a,0xe1] +[0x07,0xf2,0x2b,0xe1] +[0x0b,0xf2,0x2c,0xe1] +[0x01,0xf2,0x2d,0xe1] +[0x02,0xf2,0x2e,0xe1] +[0x03,0xf2,0x6e,0xe1] +@ CHECK: msr r8_fiq, r2 +@ CHECK: msr r9_fiq, r3 +@ CHECK: msr r10_fiq, r5 +@ CHECK: msr r11_fiq, r7 +@ CHECK: msr r12_fiq, r11 +@ CHECK: msr sp_fiq, r1 +@ CHECK: msr lr_fiq, r2 +@ CHECK: msr SPSR_fiq, r3 + +[0x04,0xf3,0x20,0xe1] +[0x09,0xf3,0x21,0xe1] +[0x0b,0xf3,0x60,0xe1] +@ CHECK: msr lr_irq, r4 +@ CHECK: msr sp_irq, r9 +@ CHECK: msr SPSR_irq, r11 + +[0x01,0xf3,0x22,0xe1] +[0x03,0xf3,0x23,0xe1] +[0x05,0xf3,0x62,0xe1] +@ CHECK: msr lr_svc, r1 +@ CHECK: msr sp_svc, r3 +@ CHECK: msr SPSR_svc, r5 + +[0x05,0xf3,0x24,0xe1] +[0x07,0xf3,0x25,0xe1] +[0x09,0xf3,0x64,0xe1] +@ CHECK: msr lr_abt, r5 +@ CHECK: msr sp_abt, r7 +@ CHECK: msr SPSR_abt, r9 + +[0x09,0xf3,0x26,0xe1] +[0x0b,0xf3,0x27,0xe1] +[0x0c,0xf3,0x66,0xe1] +@ CHECK: msr lr_und, r9 +@ CHECK: msr sp_und, r11 +@ CHECK: msr SPSR_und, r12 + +[0x02,0xf3,0x2c,0xe1] +[0x04,0xf3,0x2d,0xe1] +[0x06,0xf3,0x6c,0xe1] +@ CHECK: msr lr_mon, r2 +@ CHECK: msr sp_mon, r4 +@ CHECK: msr SPSR_mon, r6 + +[0x06,0xf3,0x2e,0xe1] +[0x08,0xf3,0x2f,0xe1] +[0x0a,0xf3,0x6e,0xe1] +@ CHECK: msr elr_hyp, r6 +@ CHECK: msr sp_hyp, r8 +@ CHECK: msr SPSR_hyp, r10 diff --git a/test/MC/Disassembler/ARM/move-banked-regs-thumb.txt b/test/MC/Disassembler/ARM/move-banked-regs-thumb.txt new file mode 100644 index 00000000000..29e91abcc7f --- /dev/null +++ b/test/MC/Disassembler/ARM/move-banked-regs-thumb.txt @@ -0,0 +1,153 @@ +@ RUN: llvm-mc -disassemble -triple thumb -mcpu=cyclone %s | FileCheck %s + +[0xe0,0xf3,0x20,0x82] +[0xe1,0xf3,0x20,0x83] +[0xe2,0xf3,0x20,0x85] +[0xe3,0xf3,0x20,0x87] +[0xe4,0xf3,0x20,0x8b] +[0xe5,0xf3,0x20,0x81] +[0xe6,0xf3,0x20,0x82] +@ CHECK: mrs r2, r8_usr +@ CHECK: mrs r3, r9_usr +@ CHECK: mrs r5, r10_usr +@ CHECK: mrs r7, r11_usr +@ CHECK: mrs r11, r12_usr +@ CHECK: mrs r1, sp_usr +@ CHECK: mrs r2, lr_usr + +[0xe8,0xf3,0x20,0x82] +[0xe9,0xf3,0x20,0x83] +[0xea,0xf3,0x20,0x85] +[0xeb,0xf3,0x20,0x87] +[0xec,0xf3,0x20,0x8b] +[0xed,0xf3,0x20,0x81] +[0xee,0xf3,0x20,0x82] +[0xfe,0xf3,0x20,0x83] +@ CHECK: mrs r2, r8_fiq +@ CHECK: mrs r3, r9_fiq +@ CHECK: mrs r5, r10_fiq +@ CHECK: mrs r7, r11_fiq +@ CHECK: mrs r11, r12_fiq +@ CHECK: mrs r1, sp_fiq +@ CHECK: mrs r2, lr_fiq +@ CHECK: mrs r3, SPSR_fiq + +[0xe0,0xf3,0x30,0x84] +[0xe1,0xf3,0x30,0x89] +[0xf0,0xf3,0x30,0x81] +@ CHECK: mrs r4, lr_irq +@ CHECK: mrs r9, sp_irq +@ CHECK: mrs r1, SPSR_irq + +[0xe2,0xf3,0x30,0x81] +[0xe3,0xf3,0x30,0x83] +[0xf2,0xf3,0x30,0x85] +@ CHECK: mrs r1, lr_svc +@ CHECK: mrs r3, sp_svc +@ CHECK: mrs r5, SPSR_svc + +[0xe4,0xf3,0x30,0x85] +[0xe5,0xf3,0x30,0x87] +[0xf4,0xf3,0x30,0x89] +@ CHECK: mrs r5, lr_abt +@ CHECK: mrs r7, sp_abt +@ CHECK: mrs r9, SPSR_abt + +[0xe6,0xf3,0x30,0x89] +[0xe7,0xf3,0x30,0x8b] +[0xf6,0xf3,0x30,0x8c] +@ CHECK: mrs r9, lr_und +@ CHECK: mrs r11, sp_und +@ CHECK: mrs r12, SPSR_und + + +[0xec,0xf3,0x30,0x82] +[0xed,0xf3,0x30,0x84] +[0xfc,0xf3,0x30,0x86] +@ CHECK: mrs r2, lr_mon +@ CHECK: mrs r4, sp_mon +@ CHECK: mrs r6, SPSR_mon + + +[0xee,0xf3,0x30,0x86] +[0xef,0xf3,0x30,0x88] +[0xfe,0xf3,0x30,0x8a] +@ CHECK: mrs r6, elr_hyp +@ CHECK: mrs r8, sp_hyp +@ CHECK: mrs r10, SPSR_hyp + + +[0x82,0xf3,0x20,0x80] +[0x83,0xf3,0x20,0x81] +[0x85,0xf3,0x20,0x82] +[0x87,0xf3,0x20,0x83] +[0x8b,0xf3,0x20,0x84] +[0x81,0xf3,0x20,0x85] +[0x82,0xf3,0x20,0x86] +@ CHECK: msr r8_usr, r2 +@ CHECK: msr r9_usr, r3 +@ CHECK: msr r10_usr, r5 +@ CHECK: msr r11_usr, r7 +@ CHECK: msr r12_usr, r11 +@ CHECK: msr sp_usr, r1 +@ CHECK: msr lr_usr, r2 + +[0x82,0xf3,0x20,0x88] +[0x83,0xf3,0x20,0x89] +[0x85,0xf3,0x20,0x8a] +[0x87,0xf3,0x20,0x8b] +[0x8b,0xf3,0x20,0x8c] +[0x81,0xf3,0x20,0x8d] +[0x82,0xf3,0x20,0x8e] +[0x93,0xf3,0x20,0x8e] +@ CHECK: msr r8_fiq, r2 +@ CHECK: msr r9_fiq, r3 +@ CHECK: msr r10_fiq, r5 +@ CHECK: msr r11_fiq, r7 +@ CHECK: msr r12_fiq, r11 +@ CHECK: msr sp_fiq, r1 +@ CHECK: msr lr_fiq, r2 +@ CHECK: msr SPSR_fiq, r3 + +[0x84,0xf3,0x30,0x80] +[0x89,0xf3,0x30,0x81] +[0x9b,0xf3,0x30,0x80] +@ CHECK: msr lr_irq, r4 +@ CHECK: msr sp_irq, r9 +@ CHECK: msr SPSR_irq, r11 + +[0x81,0xf3,0x30,0x82] +[0x83,0xf3,0x30,0x83] +[0x95,0xf3,0x30,0x82] +@ CHECK: msr lr_svc, r1 +@ CHECK: msr sp_svc, r3 +@ CHECK: msr SPSR_svc, r5 + +[0x85,0xf3,0x30,0x84] +[0x87,0xf3,0x30,0x85] +[0x99,0xf3,0x30,0x84] +@ CHECK: msr lr_abt, r5 +@ CHECK: msr sp_abt, r7 +@ CHECK: msr SPSR_abt, r9 + +[0x89,0xf3,0x30,0x86] +[0x8b,0xf3,0x30,0x87] +[0x9c,0xf3,0x30,0x86] +@ CHECK: msr lr_und, r9 +@ CHECK: msr sp_und, r11 +@ CHECK: msr SPSR_und, r12 + + +[0x82,0xf3,0x30,0x8c] +[0x84,0xf3,0x30,0x8d] +[0x96,0xf3,0x30,0x8c] +@ CHECK: msr lr_mon, r2 +@ CHECK: msr sp_mon, r4 +@ CHECK: msr SPSR_mon, r6 + +[0x86,0xf3,0x30,0x8e] +[0x88,0xf3,0x30,0x8f] +[0x9a,0xf3,0x30,0x8e] +@ CHECK: msr elr_hyp, r6 +@ CHECK: msr sp_hyp, r8 +@ CHECK: msr SPSR_hyp, r10 -- 2.11.0