From f57b62b5fcb619f4a892e6f4036a440603292b47 Mon Sep 17 00:00:00 2001 From: astoria-d Date: Fri, 21 Jun 2013 14:30:53 +0900 Subject: [PATCH] - cmp bug fixed. - tay supported. --- simulation/cpu/alu.vhd | 3 +++ simulation/cpu/cpu_registers.vhd | 3 ++- simulation/cpu/decoder.vhd | 3 +++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd index fcaf7c2..48af893 100644 --- a/simulation/cpu/alu.vhd +++ b/simulation/cpu/alu.vhd @@ -757,6 +757,9 @@ end procedure; else carry_out <= '0'; end if; + set_n(res(dsize - 1 downto 0)); + set_z(res(dsize - 1 downto 0)); + elsif sel = ALU_SL then ---- elsif sel = ALU_SR then diff --git a/simulation/cpu/cpu_registers.vhd b/simulation/cpu/cpu_registers.vhd index 36a133f..6481dc8 100644 --- a/simulation/cpu/cpu_registers.vhd +++ b/simulation/cpu/cpu_registers.vhd @@ -360,7 +360,8 @@ begin dff_inst : d_flip_flop generic map (dsize) port map(clk, '1', res_n, we_n, d, status_val); - main_p : process (clk, res_n, we_n, dec_val, int_dbus) + main_p : process (clk, res_n, we_n, dec_val, int_dbus, + alu_n, alu_v, alu_z, alu_c) variable tmp : std_logic_vector (dsize - 1 downto 0); begin -- SR Flags (bit 7 to bit 0): diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd index 652d621..67b70a2 100644 --- a/simulation/cpu/decoder.vhd +++ b/simulation/cpu/decoder.vhd @@ -749,6 +749,9 @@ end procedure; elsif instruction = conv_std_logic_vector(16#a8#, dsize) then d_print("tay"); set_nz_from_bus; + single_inst; + front_oe(acc_cmd, '0'); + front_we(y_cmd, '0'); elsif instruction = conv_std_logic_vector(16#ba#, dsize) then d_print("tsx"); -- 2.11.0