From f5c667f88ca4b6f3870b7be3dd5b974c6b754e6e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 13 Nov 2017 05:33:35 +0000 Subject: [PATCH] AMDGPU: Preserve nuw in shl add ptr combine git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318017 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIISelLowering.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 73cd6971660..0be8e810545 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5229,7 +5229,12 @@ SDValue SITargetLowering::performSHLPtrCombine(SDNode *N, SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1); SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32); - return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset); + SDNodeFlags Flags; + Flags.setNoUnsignedWrap(N->getFlags().hasNoUnsignedWrap() && + (N0.getOpcode() == ISD::OR || + N0->getFlags().hasNoUnsignedWrap())); + + return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset, Flags); } SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N, -- 2.11.0