From f60b0de42a8bb5ead55022c6342527bf31f8fbb8 Mon Sep 17 00:00:00 2001 From: Kit Barton Date: Mon, 9 Feb 2015 17:03:18 +0000 Subject: [PATCH] This change implements the following three logical vector operations: veqv (vector equivalence) vnand vorc I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions. Phabricator review: http://reviews.llvm.org/D7469 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228580 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstrAltivec.td | 25 ++++++++++++++++++++ test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll | 27 ++++++++++++++++++++++ .../MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt | 9 ++++++++ test/MC/PowerPC/ppc64-encoding-vmx.s | 9 ++++++++ 4 files changed, 70 insertions(+) create mode 100644 test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 9379bad7317..f17f251377e 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -968,4 +968,29 @@ def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), "vpopcntd $vD, $vB", IIC_VecGeneral, [(set v2i64:$vD, (ctpop v2i64:$vB))]>; + +let isCommutable = 1 in { +let AddedComplexity = 500 in { +// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the +// VSX equivalents. We need to fix this up at some point. Two possible +// solutions for this problem: +// 1. Disable Altivec patterns that compete with VSX patterns using the +// !HasVSX predicate. This essentially favours VSX over Altivec, in +// hopes of reducing register pressure (larger register set using VSX +// instructions than VMX instructions) +// 2. Employ a more disciplined use of AddedComplexity, which would provide +// more fine-grained control than option 1. This would be beneficial +// if we find situations where Altivec is really preferred over VSX. +def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), + "veqv $vD, $vA, $vB", IIC_VecGeneral, + [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>; +def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), + "vnand $vD, $vA, $vB", IIC_VecGeneral, + [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>; +def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), + "vorc $vD, $vA, $vB", IIC_VecGeneral, + [(set v4i32:$vD, (or v4i32:$vA, + (vnot_ppc v4i32:$vB)))]>; +} // AddedComplexity = 500 +} // isCommutable } // end HasP8Altivec diff --git a/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll b/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll new file mode 100644 index 00000000000..44feadbf39b --- /dev/null +++ b/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll @@ -0,0 +1,27 @@ +; Check the miscellaneous logical vector operations added in P8 +; +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s +; Test x eqv y +define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind { + %tmp = xor <4 x i32> %x, %y + %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %ret_val +; CHECK: veqv 2, 2, 3 +} + +; Test x vnand y +define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind { + %tmp = and <4 x i32> %x, %y + %ret_val = xor <4 x i32> %tmp, + ret <4 x i32> %ret_val +; CHECK: vnand 2, 2, 3 +} + +; Test x vorc y +define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind { + %tmp = xor <4 x i32> %y, + %ret_val = or <4 x i32> %x, %tmp + ret <4 x i32> %ret_val +; CHECK: vorc 2, 2, 3 +} diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt index 4f12a6cd166..fe62fdf3c71 100644 --- a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt @@ -378,6 +378,15 @@ # CHECK: vandc 2, 3, 4 0x10 0x43 0x24 0x44 +# CHECK: veqv 2, 3, 4 +0x10 0x43 0x26 0x84 + +# CHECK: vnand 2, 3, 4 +0x10 0x43 0x25 0x84 + +# CHECK: vorc 2, 3, 4 +0x10 0x43 0x25 0x44 + # CHECK: vnor 2, 3, 4 0x10 0x43 0x25 0x04 diff --git a/test/MC/PowerPC/ppc64-encoding-vmx.s b/test/MC/PowerPC/ppc64-encoding-vmx.s index 09e5ecc5e77..7641d1d7ac0 100644 --- a/test/MC/PowerPC/ppc64-encoding-vmx.s +++ b/test/MC/PowerPC/ppc64-encoding-vmx.s @@ -408,6 +408,15 @@ # CHECK-BE: vandc 2, 3, 4 # encoding: [0x10,0x43,0x24,0x44] # CHECK-LE: vandc 2, 3, 4 # encoding: [0x44,0x24,0x43,0x10] vandc 2, 3, 4 +# CHECK-BE: veqv 2, 3, 4 # encoding: [0x10,0x43,0x26,0x84] +# CHECK-LE: veqv 2, 3, 4 # encoding: [0x84,0x26,0x43,0x10] + veqv 2, 3, 4 +# CHECK-BE: vnand 2, 3, 4 # encoding: [0x10,0x43,0x25,0x84] +# CHECK-LE: vnand 2, 3, 4 # encoding: [0x84,0x25,0x43,0x10] + vnand 2, 3, 4 +# CHECK-BE: vorc 2, 3, 4 # encoding: [0x10,0x43,0x25,0x44] +# CHECK-LE: vorc 2, 3, 4 # encoding: [0x44,0x25,0x43,0x10] + vorc 2, 3, 4 # CHECK-BE: vnor 2, 3, 4 # encoding: [0x10,0x43,0x25,0x04] # CHECK-LE: vnor 2, 3, 4 # encoding: [0x04,0x25,0x43,0x10] vnor 2, 3, 4 -- 2.11.0