From f6450bcb6b2d3e4beae77141edce9e99cb8c277e Mon Sep 17 00:00:00 2001 From: Leif Lindholm Date: Fri, 8 Jan 2021 18:51:50 +0000 Subject: [PATCH] target/arm: make ARMCPU.clidr 64-bit MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit 32, as well as adding a Ttype field when FEAT_MTE is implemented. Extend the clidr field to be able to hold this context. Signed-off-by: Leif Lindholm Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues Message-id: 20210108185154.8108-3-leif@nuviainc.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ed3e9fe2e4..fdbfcec2b0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -938,7 +938,7 @@ struct ARMCPU { uint32_t id_afr0; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint32_t clidr; + uint64_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. -- 2.11.0