From f8075c1cdc79002a0a8ce141c0c2e8c627a46c66 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 3 May 2019 06:39:41 -0400 Subject: [PATCH] media: v4l: fwnode: C-PHY has no clock lane C-PHY doesn't use a clock lane, hence the test for the clock lane when there isn't one is faulty. Rework the test for the conflicting clock lane. Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/v4l2-core/v4l2-fwnode.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index ea1ed88f9dc8..dea8917fd912 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -212,10 +212,10 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode, have_clk_lane = true; } - if (lanes_used & BIT(clock_lane)) { - if (have_clk_lane || !use_default_lane_mapping) - pr_warn("duplicated lane %u in clock-lanes, using defaults\n", - v); + if (have_clk_lane && lanes_used & BIT(clock_lane) && + !use_default_lane_mapping) { + pr_warn("duplicated lane %u in clock-lanes, using defaults\n", + v); use_default_lane_mapping = true; } -- 2.11.0