From fac9941e57013127593a47e02e7e88f56c9be2a4 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 23 Jan 2020 14:10:04 -0500 Subject: [PATCH] AMDGPU: Fix ubsan error Since register classes go up to 1024, 32 elements, all masks bits are needed and a 32-bit shift by 32 is illegal. We didn't have any instructions theoretically using a 32 element VGPR before d1dbb5e4718a8f845abf0783513a33a55429470b --- llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp index 76593bc0e5a..fef70738349 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp @@ -168,7 +168,7 @@ private: // 8 banks for SGPRs. // Registers already processed and recorded in RegsUsed are excluded. // If Bank is not -1 assume Reg:SubReg to belong to that Bank. - unsigned getRegBankMask(unsigned Reg, unsigned SubReg, int Bank); + uint32_t getRegBankMask(unsigned Reg, unsigned SubReg, int Bank); // Return number of stalls in the instructions. // UsedBanks has bits set for the banks used by all operands. @@ -292,7 +292,7 @@ unsigned GCNRegBankReassign::getPhysRegBank(unsigned Reg) const { return Reg % NUM_SGPR_BANKS + SGPR_BANK_OFFSET; } -unsigned GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, +uint32_t GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, int Bank) { if (Register::isVirtualRegister(Reg)) { if (!VRM->isAssignedReg(Reg)) @@ -313,7 +313,7 @@ unsigned GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, if (TRI->hasVGPRs(RC)) { // VGPRs have 4 banks assigned in a round-robin fashion. Reg -= AMDGPU::VGPR0; - unsigned Mask = (1 << Size) - 1; + uint32_t Mask = maskTrailingOnes(Size); unsigned Used = 0; // Bitmask lacks an extract method for (unsigned I = 0; I < Size; ++I) @@ -321,7 +321,7 @@ unsigned GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, Used |= 1 << I; RegsUsed.set(Reg, Reg + Size); Mask &= ~Used; - Mask <<= (Bank == -1) ? Reg % NUM_VGPR_BANKS : unsigned(Bank); + Mask <<= (Bank == -1) ? Reg % NUM_VGPR_BANKS : uint32_t(Bank); return (Mask | (Mask >> NUM_VGPR_BANKS)) & VGPR_BANK_MASK; } @@ -388,7 +388,7 @@ unsigned GCNRegBankReassign::analyzeInst(const MachineInstr& MI, } } - unsigned Mask = getRegBankMask(R, Op.getSubReg(), + uint32_t Mask = getRegBankMask(R, Op.getSubReg(), (Reg == R) ? ShiftedBank : -1); StallCycles += countPopulation(UsedBanks & Mask); UsedBanks |= Mask; -- 2.11.0