From fb33552f72663e2a860d16a9ff27deb72159ceae Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Wed, 24 Aug 2016 02:32:29 +0000 Subject: [PATCH] TargetSchedule: Do not consider subregister definitions as reads. We should not consider subregister definitions as reads for schedule model purposes (they are just modeled as reads of the overal vreg for liveness calculation purposes, the CPU instructions are not actually reading). Unfortunately I cannot submit a test for this as it requires a target which uses ReadAdvance annotation in the scheduling model and has subregister liveness enabled at the same time, which is only the case on an out of tree target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279604 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/TargetSchedule.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/CodeGen/TargetSchedule.cpp b/lib/CodeGen/TargetSchedule.cpp index 022e912aa84..83e52d33535 100644 --- a/lib/CodeGen/TargetSchedule.cpp +++ b/lib/CodeGen/TargetSchedule.cpp @@ -144,7 +144,7 @@ static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) { unsigned UseIdx = 0; for (unsigned i = 0; i != UseOperIdx; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.readsReg()) + if (MO.isReg() && MO.readsReg() && !MO.isDef()) ++UseIdx; } return UseIdx; -- 2.11.0