From fb6bbafc0f19385fb257ee073ed13dcaf613f2f8 Mon Sep 17 00:00:00 2001 From: Tom Lendacky Date: Fri, 30 Sep 2022 10:14:30 -0500 Subject: [PATCH] i386/cpu: Update how the EBX register of CPUID 0x8000001F is set Update the setting of CPUID 0x8000001F EBX to clearly document the ranges associated with fields being set. Fixes: 6cb8f2a663 ("cpu/i386: populate CPUID 0x8000_001F when SEV is active") Signed-off-by: Tom Lendacky Reviewed-by: Dr. David Alan Gilbert Message-Id: <5822fd7d02b575121380e1f493a8f6d9eba2b11a.1664550870.git.thomas.lendacky@amd.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2e30e348a1..73dd99374a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6000,8 +6000,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (sev_enabled()) { *eax = 0x2; *eax |= sev_es_enabled() ? 0x8 : 0; - *ebx = sev_get_cbit_position(); - *ebx |= sev_get_reduced_phys_bits() << 6; + *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ + *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ } break; default: -- 2.11.0