From fee3eae1334a454a8c2e16313a374cc53ff722d8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 22 Nov 2021 10:39:05 +0000 Subject: [PATCH] arm64: dts: renesas: r9a07g044: Rename SDHI clocks Rename the below SDHI clocks to match with the clocks used in driver. imclk->core clk_hs->clkh imclk2->cd Also re-arrange the clocks to match with the sorting order used in the binding document. Signed-off-by: Biju Das Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20211122103905.14439-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index be9e5c495553..71f1701a1b66 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -613,10 +613,10 @@ interrupts = , ; clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; - clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -629,10 +629,10 @@ interrupts = , ; clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, - <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; - clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled"; -- 2.11.0