From fffe3634933471ee9805412ffa221080c9e9e8fd Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Fri, 11 Jan 2013 18:12:39 +0000 Subject: [PATCH] For inline asm: - recognize string "{memory}" in the MI generation - mark as mayload/maystore when there's a memory clobber constraint. PR14859. Patch by Krzysztof Parzyszek git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172228 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MachineInstr.cpp | 6 +++++- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 6 ++++++ lib/CodeGen/SelectionDAG/TargetLowering.cpp | 10 +++++++--- test/CodeGen/Generic/inline-asm-mem-clobber.ll | 21 +++++++++++++++++++++ 4 files changed, 39 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/Generic/inline-asm-mem-clobber.ll diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index df82a17a2b2..8f7c5fd0224 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -1476,10 +1476,14 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { OS << " "; getOperand(InlineAsm::MIOp_AsmString).print(OS, TM); - // Print HasSideEffects, IsAlignStack + // Print HasSideEffects, MayLoad, MayStore, IsAlignStack unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); if (ExtraInfo & InlineAsm::Extra_HasSideEffects) OS << " [sideeffect]"; + if (ExtraInfo & InlineAsm::Extra_MayLoad) + OS << " [mayload]"; + if (ExtraInfo & InlineAsm::Extra_MayStore) + OS << " [maystore]"; if (ExtraInfo & InlineAsm::Extra_IsAlignStack) OS << " [alignstack]"; if (getInlineAsmDialect() == InlineAsm::AD_ATT) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 599ef2c7cc9..4e07fd379cb 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5948,6 +5948,10 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { // Compute the constraint code and ConstraintType to use. TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); + if (OpInfo.ConstraintType == TargetLowering::C_Memory && + OpInfo.Type == InlineAsm::isClobber) + continue; + // If this is a memory input, and if the operand is not indirect, do what we // need to to provide an address for the memory input. if (OpInfo.ConstraintType == TargetLowering::C_Memory && @@ -6051,6 +6055,8 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { ExtraInfo |= InlineAsm::Extra_MayLoad; else if (OpInfo.Type == InlineAsm::isOutput) ExtraInfo |= InlineAsm::Extra_MayStore; + else if (OpInfo.Type == InlineAsm::isClobber) + ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); } } diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index d2da9b728d2..35a11b40cae 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3068,7 +3068,9 @@ PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { TargetLowering::ConstraintType TargetLowering::getConstraintType(const std::string &Constraint) const { - if (Constraint.size() == 1) { + unsigned S = Constraint.size(); + + if (S == 1) { switch (Constraint[0]) { default: break; case 'r': return C_RegisterClass; @@ -3097,9 +3099,11 @@ TargetLowering::getConstraintType(const std::string &Constraint) const { } } - if (Constraint.size() > 1 && Constraint[0] == '{' && - Constraint[Constraint.size()-1] == '}') + if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') { + if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}" + return C_Memory; return C_Register; + } return C_Unknown; } diff --git a/test/CodeGen/Generic/inline-asm-mem-clobber.ll b/test/CodeGen/Generic/inline-asm-mem-clobber.ll new file mode 100644 index 00000000000..e523d031dc6 --- /dev/null +++ b/test/CodeGen/Generic/inline-asm-mem-clobber.ll @@ -0,0 +1,21 @@ +; RUN: llc -O2 < %s | FileCheck %s + +@G = common global i32 0, align 4 + +define i32 @foo(i8* %p) nounwind uwtable { +entry: + %p.addr = alloca i8*, align 8 + %rv = alloca i32, align 4 + store i8* %p, i8** %p.addr, align 8 + store i32 0, i32* @G, align 4 + %0 = load i8** %p.addr, align 8 +; CHECK: blah + %1 = call i32 asm "blah", "=r,r,~{memory}"(i8* %0) nounwind +; CHECK: @G + store i32 %1, i32* %rv, align 4 + %2 = load i32* %rv, align 4 + %3 = load i32* @G, align 4 + %add = add nsw i32 %2, %3 + ret i32 %add +} + -- 2.11.0