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2023-03-02	Palmer Dabbelt	Merge patch series "RISCVCPUConfig related cleanups" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Daniel Henrique...	target/riscv/csr.c: avoid env_archcpu() usages when... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Daniel Henrique...	target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Daniel Henrique...	target/riscv/csr.c: simplify mctr() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Daniel Henrique...	target/riscv/csr.c: use env_archcpu() in ctr() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Palmer Dabbelt	Merge patch series "target/riscv: Add support for Svadu... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Weiwei Li	target/riscv: Export Svadu property Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Weiwei Li	target/riscv: Add *envcfg.HADE related check in address... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Weiwei Li	target/riscv: Add *envcfg.PBMTE related check in address... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Weiwei Li	target/riscv: Add csr support for svadu Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Weiwei Li	target/riscv: Fix the relationship of PBMTE/STCE fields... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Weiwei Li	target/riscv: Fix the relationship between menvcfg... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	hw/riscv: Move the dtb load bits outside of create_fdt() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	hw/riscv: Skip re-generating DT nodes for a given DTB Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Weiwei Li	target/riscv: Add support for Zicond extension Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Christoph Müllner	RISC-V: XTheadMemPair: Remove register restrictions... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Shaobo Song	target/riscv: Fix checking of whether instruciton at... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Palmer Dabbelt	Merge patch series "target/riscv: Various fixes to... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Group all predicate() routines together Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Drop priv level check in mseccfg predicate() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Allow debugger to access sstc CSRs Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Allow debugger to access {h, s}stateen... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Allow debugger to access seed CSR Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Allow debugger to access user timer and... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: gdbstub: Drop the vector CSRs in riscv... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: gdbstub: Turn on debugger mode before... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Avoid reporting odd-numbered pmpcfgX... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Simplify getting RISCVCPU pointer from env Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Simplify {read, write}_pmpcfg() a little bit Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Use 'bool' type for read_only Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Coding style fixes in csr.c Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: gdbstub: Do not generate CSR XML if Zicsr... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: gdbstub: Minor change for better readability Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Use g_assert() for the predicate() NULL... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: Add some comments to clarify the priority... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-02	Bin Meng	target/riscv: gdbstub: Check priv spec version before... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Palmer Dabbelt	Merge patch series "target/riscv: Some updates to float... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Palmer Dabbelt	Merge patch series "make write_misa a no-op and FEATURE_... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Expose properties for Zv* extensions Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Simplify check for EEW = 64 in trans_rvv... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Fix check for vector load/store instructions... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Add support for Zvfh/zvfhmin extensions Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Remove redundunt check for zve32f and... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Replace check for F/D to Zve32f/Zve64d... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Simplify check for Zve32f and Zve64f Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Indent fixes in cpu.c Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Add property check for Zvfh{min} extensions Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Fix relationship between V, Zve*, F and D Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Add cfg properties for Zv* extensions Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Simplify the check for Zfhmin and Zhinxmin Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Fix the relationship between Zhinxmin... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Weiwei Li	target/riscv: Fix the relationship between Zfhmin and Zfh Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	target/riscv/cpu: remove CPUArchState::features and... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	target/riscv: remove RISCV_FEATURE_MMU Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	target/riscv: remove RISCV_FEATURE_PMP Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	target/riscv: remove RISCV_FEATURE_EPMP Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	target/riscv/cpu.c: error out if EPMP is enabled without PMP Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	target/riscv: remove RISCV_FEATURE_DEBUG Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	target/riscv: allow MISA writes as experimental Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	target/riscv: do not mask unsupported QEMU extensions... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-03-01	Daniel Henrique...	target/riscv: introduce riscv_cpu_cfg() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-02-23	LIU Zhiwei	target/riscv: Fix vslide1up.vf and vslide1down.vf Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-02-23	Daniel Henrique...	target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-02-23	Himanshu Chauhan	target/riscv: Smepmp: Skip applying default rules when... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-02-23	Alistair Francis	MAINTAINERS: Add some RISC-V reviewers Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-02-23	Frank Chang	target/riscv: Remove privileged spec version restriction... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-02-16	Daniel Henrique...	hw/riscv/boot.c: make riscv_load_initrd() static Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-02-16	Daniel Henrique...	hw/riscv/boot.c: consolidate all kernel init in riscv_load_k... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-02-16	Daniel Henrique...	hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree

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