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2019-11-13	Christoph Hellwig	riscv: poison SBI calls for M-mode Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-11-13	Damien Le Moal	riscv: don't allow selecting SBI based drivers for... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-11-05	Christoph Hellwig	riscv: abstract out CSR names for supervisor vs machine... and Paul Walmsley <paul.walmsley@sifive.com>. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-11-05	Paul Walmsley	riscv: separate MMIO functions into their own header... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-11-05	Christoph Hellwig	riscv: enter WFI in default_power_off() if SBI does... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-30	Palmer Dabbelt	MAINTAINERS: Change to my personal email address Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Yash Shah	RISC-V: Add PCIe I/O BAR memory mapping Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Paul Walmsley	riscv: for C functions called only from assembly, mark... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Paul Walmsley	riscv: fp: add missing __user pointer annotations Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Paul Walmsley	riscv: add missing header file includes Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Paul Walmsley	riscv: mark some code and data as file-static Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Paul Walmsley	riscv: init: merge split string literals in preprocessor... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-28	Paul Walmsley	riscv: add prototypes for assembly language functions... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-25	Christoph Hellwig	riscv: cleanup do_trap_break Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-23	Christoph Hellwig	riscv: cleanup <asm/bug.h> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-23	Kefeng Wang	riscv: Fix undefined reference to vmemmap_populate_basepages Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-23	Kefeng Wang	riscv: Fix implicit declaration of 'page_to_section' Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-23	David Abdurachmanov	riscv: fix fs/proc/kcore.c compilation with sparsemem... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-16	Greentime Hu	RISC-V: fix virtual address overlapped in FIXADDR_START... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-14	Paul Walmsley	riscv: tlbflush: remove confusing comment on local_flush_tlb... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-14	Paul Walmsley	riscv: dts: HiFive Unleashed: add default chosen/stdout... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-14	Vincent Chen	riscv: remove the switch statement in do_trap_break() Suggested-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-09	Valentin Schneider	RISC-V: entry: Remove unneeded need_resched() loop Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-07	Vincent Chen	riscv: Correct the handling of unexpected ebreak in... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-07	Vincent Chen	riscv: avoid sending a SIGTRAP to a user thread trapped... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-07	Vincent Chen	riscv: avoid kernel hangs when trapped in BUG() Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-01	Albert Ou	riscv: Fix memblock reservation for device tree blob Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-10-01	Palmer Dabbelt	RISC-V: Clear load reservations while restoring hart... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-20	Vincent Chen	riscv: Avoid interrupts being erroneously enabled in... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-20	Bin Meng	riscv: dts: sifive: Drop "clock-frequency" property... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-20	Bin Meng	riscv: dts: sifive: Add ethernet0 to the aliases node Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-20	Atish Patra	RISC-V: Export kernel symbols for kvm Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-20	Anup Patel	KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-20	Xiang Wang	arch/riscv: disable excess harts before picking main... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-19	Anup Patel	RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-19	Greentime Hu	RISC-V: Fix building error when CONFIG_SPARSEMEM_MANUAL=y Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-19	Yash Shah	riscv: dts: Add DT support for SiFive FU540 PWM driver Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-14	Paul Walmsley	riscv: modify the Image header to improve compatibility... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-05	Christoph Hellwig	irqchip/sifive-plic: set max threshold for ignored... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-05	Christoph Hellwig	riscv: move the TLB flush logic out of line Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-05	Christoph Hellwig	riscv: don't use the rdtime(h) pseudo-instructions Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-05	Christoph Hellwig	riscv: cleanup riscv_cpuid_to_hartid_mask Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-05	Christoph Hellwig	riscv: optimize send_ipi_single Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-05	Christoph Hellwig	riscv: cleanup send_ipi_mask Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-05	Christoph Hellwig	riscv: refactor the IPI code Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-05	Mao Han	riscv: Add support for libdw Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-05	Mao Han	riscv: Add support for perf registers sampling Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-09-04	Mao Han	riscv: Add perf callchain support Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-31	Masahiro Yamada	riscv: add arch/riscv/Kbuild Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-30	Logan Gunthorpe	RISC-V: Implement sparsemem Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-30	Bin Meng	riscv: Using CSR numbers to access CSRs Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-30	Paul Walmsley	Merge tag 'common/for-v5.4-rc1/cpu-topology' into for...	commit \| commitdiff \| tree
2019-08-28	Anup Patel	RISC-V: Fix FIXMAP area corruption on RV32 systems Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-14	Vincent Chen	riscv: Make __fstate_clean() work correctly. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-14	Vincent Chen	riscv: Correct the initialized flow of FP register Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-14	Alistair Francis	riscv: defconfig: Update the defconfig Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-14	Alistair Francis	riscv: rv32_defconfig: Update the defconfig Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-13	Paul Walmsley	riscv: fix flush_tlb_range() end address for flush_tlb_page() Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-08	Paul Walmsley	dt-bindings: riscv: fix the schema compatible string... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-08	Paul Walmsley	dt-bindings: riscv: remove obsolete cpus.txt Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-08	Palmer Dabbelt	RISC-V: Remove udivdi3 Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-08	Paul Walmsley	riscv: delay: use do_div() instead of __udivdi3() Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-08	Atish Patra	dt-bindings: Update the riscv,isa string description Suggested-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-08-06	Atish Patra	RISC-V: Remove per cpu clocksource Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-31	Paul Walmsley	riscv: defconfig: align RV64 defconfig to the output... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-31	Paul Walmsley	riscv: dts: fu540-c000: drop "timebase-frequency" Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-31	Mao Han	riscv: Fix perf record without libelf support Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Yash Shah	riscv: dts: Add DT node for SiFive FU540 Ethernet controller... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Wesley Terpstra	riscv: include generic support for MSI irqdomains Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Palmer Dabbelt	MAINTAINERS: Add Paul as a RISC-V maintainer Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Sudeep Holla	MAINTAINERS: Add an entry for generic architecture... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Sudeep Holla	base: arch_topology: update Kconfig help description Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Atish Patra	RISC-V: Parse cpu topology during boot. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Atish Patra	arm: Use common cpu_topology structure and functions. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Atish Patra	cpu-topology: Move cpu topology code to common code. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Atish Patra	dt-binding: cpu-topology: Move cpu-map to a common... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-22	Sudeep Holla	Documentation: DT: arm: add support for sockets defining... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-19	Paul Walmsley	riscv: enable sys_clone3 syscall for rv64 Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-18	Paul Walmsley	riscv: fix build break after macro-to-function conversion... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-11	Atish Patra	RISC-V: Add an Image header that boot loader can parse. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-09	Anup Patel	RISC-V: Setup initial page tables in two stages Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-04	Christoph Hellwig	riscv: remove free_initrd_mem Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-04	Yash Shah	riscv: ccache: Remove unused variable Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-03	Alexandre Ghiti	riscv: Introduce huge page support for 32/64bit kernel Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-03	Alexandre Ghiti	x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-01	Anup Patel	RISC-V: Fix memory reservation in setup_bootmem() Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-01	Loys Ollivier	riscv: defconfig: enable SOC_SIFIVE Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-01	Loys Ollivier	riscv: select SiFive platform drivers with SOC_SIFIVE Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-01	Loys Ollivier	arch: riscv: add config option for building SiFive... Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-01	Andy Lutomirski	riscv: Remove gate area stubs Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-01	Paul Walmsley	MAINTAINERS: change the arch/riscv git tree to the... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-01	Paul Walmsley	MAINTAINERS: don't automatically patches involving... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-07-01	Anup Patel	RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-06-26	ShihPo Hung	riscv: mm: Fix code comment Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Paul Walmsley	dt-bindings: clock: sifive: add MIT license as an option... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Paul Walmsley	dt-bindings: riscv: resolve 'make dt_binding_check... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Yash Shah	riscv: dts: Re-organize the DT nodes Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-06-26	Atish Patra	RISC-V: defconfig: enable MMC & SPI for RISC-V Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-06-17	Rolf Eike Beer	riscv: remove unused barrier defines Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
2019-06-17	ShihPo Hung	riscv: mm: synchronize MMU after pte change Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Cc: Paul Walmsley <paul.walmsley@sifive.com>	commit \| commitdiff \| tree
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