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target/openrisc: Enable MTTCG
2022-09-04
Stafford Horne
target/openrisc: Enable MTTCG
Signed-off-by: Stafford Horne <
shorne@gmail.com
>
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2022-09-04
Stafford Horne
target/openrisc: Add interrupted CPU to log
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-09-04
Stafford Horne
hw/openrisc: Initialize timer time at startup
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-09-04
Stafford Horne
hw/openrisc: Add PCI bus support to virt
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-09-04
Stafford Horne
hw/openrisc: Add the OpenRISC virtual machine
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-09-04
Stafford Horne
goldfish_rtc: Add big-endian property
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-09-04
Stafford Horne
target/openrisc: Fix memory reading in debugger
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-09-04
Stafford Horne
hw/openrisc: Split re-usable boot time apis out to...
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-05-15
Stafford Horne
target/openrisc: Do not reset delay slot flag on early...
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-02-26
Stafford Horne
hw/openrisc/openrisc_sim: Add support for initrd loading
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-02-26
Stafford Horne
hw/openrisc/openrisc_sim: Add automatic device tree...
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-02-25
Stafford Horne
hw/openrisc/openrisc_sim: Increase max_cpus to 4
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-02-25
Stafford Horne
hw/openrisc/openrisc_sim: Use IRQ splitter when connecting...
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-02-25
Stafford Horne
hw/openrisc/openrisc_sim: Parameterize initialization
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2022-02-25
Stafford Horne
hw/openrisc/openrisc_sim: Create machine state for...
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2020-01-17
Stafford Horne
target/openrisc: Fix FPCSR mask to allow setting DZF
Signed-off-by: Stafford Horne <
shorne@gmail.com
>
Message-Id: <20200110212843.27335-1-
shorne@gmail.com
>
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2018-07-03
Stafford Horne
target/openrisc: Fix writes to interrupt mask register
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2018-07-03
Stafford Horne
target/openrisc: Fix delay slot exception flag to match...
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-10-20
Stafford Horne
openrisc: Only kick cpu on timeout, not on update
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-10-20
Stafford Horne
openrisc: Initial SMP support
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-10-20
Stafford Horne
openrisc/cputimer: Perparation for Multicore
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-10-20
Stafford Horne
target/openrisc: Make coreid and numcores variable
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-10-20
Stafford Horne
openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-05-04
Stafford Horne
target/openrisc: Support non-busy idle state using...
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-05-04
Stafford Horne
target/openrisc: Remove duplicate features property
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-05-04
Stafford Horne
target/openrisc: Implement full vmstate serialization
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-05-04
Stafford Horne
migration: Add VMSTATE_STRUCT_2DARRAY()
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-05-04
Stafford Horne
target/openrisc: implement shadow registers
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-05-04
Stafford Horne
migration: Add VMSTATE_UINTTL_2DARRAY()
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-05-04
Stafford Horne
target/openrisc: add numcores and coreid support
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-05-04
Stafford Horne
target/openrisc: Fixes for memory debugging
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-04-21
Stafford Horne
MAINTAINERS: Add myself as openrisc maintainer
Signed-off-by: Stafford Horne <
shorne@gmail.com
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2017-02-13
Stafford Horne
target/openrisc: Fix exception handling status registers
Signed-off-by: Stafford Horne <
shorne@gmail.com
>
Message-Id: <20170113220028.29687-1-
shorne@gmail.com
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