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hw/avr/atmega.c: use the avr51 cpu for atmega1280
2021-05-11
LIU Zhiwei
target/riscv: Fixup saturate subtract function
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-08-28
LIU Zhiwei
softfloat: Define misc operations for bfloat16
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-08-28
LIU Zhiwei
softfloat: Define convert operations for bfloat16
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-08-28
LIU Zhiwei
softfloat: Define operations for bfloat16
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-08-22
LIU Zhiwei
target/riscv: check before allocating TCG temps
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-08-22
LIU Zhiwei
target/riscv: Clean up fmv.w.x
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LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-22
LIU Zhiwei
target/riscv: fix vector index load/store constraints
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-22
LIU Zhiwei
target/riscv: Quiet Coverity complains about vamo*
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-15
LIU Zhiwei
fpu/softfloat: fix up float16 nan recognition
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: configure and turn on vector extension...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector compress instruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector register gather instruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector slide instructions
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LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: floating-point scalar move instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: integer scalar move instruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: integer extract instruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector element index instruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector iota instruction
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LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: set-X-first mask bit
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vmfirst find-first-set mask bit
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector mask population count vmpopc
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector mask-register logical instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector widening floating-point reduction...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width floating-point reduction...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector wideing integer reduction instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width integer reduction...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: narrowing floating-point/integer type...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: widening floating-point/integer type...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector floating-point/integer type-convert...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector floating-point merge instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector floating-point classify instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector floating-point compare instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector floating-point sign-injection...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector floating-point min/max instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector floating-point square-root instruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector widening floating-point fused...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width floating-point fused...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector widening floating-point multiply
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width floating-point multiply...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector widening floating-point add/subtract...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width floating-point add...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector narrowing fixed-point clip instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width scaling shift instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector widening saturating scaled multiply-add
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width fractional multiply...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width averaging add and...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width saturating add and...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector integer merge and move instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector widening integer multiply-add...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width integer multiply...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector widening integer multiply instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector integer divide instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width integer multiply...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector integer min/max instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector integer comparison instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector narrowing integer right shift...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width bit shift instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector bitwise logical instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector integer add-with-carry / subtract...
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector widening integer add and subtract
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: vector single-width integer add and subtract
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: add vector amo operations
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: add fault-only-first unit stride load
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: add vector index load and store instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: add vector stride load and store instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: add an internals.h header
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: add vector configure instruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: support vector extension csr
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: implementation-defined constant parameters
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
target/riscv: add vector extension field in CPURISCVState
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-04-29
LIU Zhiwei
linux-user/riscv: fix up struct target_ucontext definition
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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