2022-02-16 | Yu Li | docs/system: riscv: Update description of CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Weiwei Li | target/riscv: add support for svpbmt extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Weiwei Li | target/riscv: add support for svinval extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Weiwei Li | target/riscv: add support for svnapot extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Weiwei Li | target/riscv: add PTE_A/PTE_D/PTE_U bits check for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Guo Ren | target/riscv: Ignore reserved bits in PTE for RV64 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | hw/intc: Add RISC-V AIA APLIC device emulation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Allow users to force enable AIA CSRs... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | hw/riscv: virt: Use AIA INTC compatible string when... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Implement AIA IMSIC interface CSRs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Implement AIA xiselect and xireg CSRs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Implement AIA mtopi, stopi, and vstopi... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Implement AIA interrupt filtering CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Implement AIA hvictl and hviprioX CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Implement AIA CSRs for 64 local interrupts... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Implement AIA local interrupt priorities Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Allow AIA device emulation to set ireg... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Add defines for AIA CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Add AIA cpu feature Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Allow setting CPU feature from machine... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Improve delivery of guest external interrupts Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Implement hgeie and hgeip CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Implement SGEIP bit in hip and hie CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Anup Patel | target/riscv: Fix trap cause for RV32 HS-mode CSR access... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | LIU Zhiwei | target/riscv: Fix vill field write in vtype Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Philipp Tomsich | target/riscv: add a MAINTAINERS entry for XVentanaCondOps Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Philipp Tomsich | target/riscv: Add XVentanaCondOps custom extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Philipp Tomsich | target/riscv: iterate over a table of decoders Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Philipp Tomsich | target/riscv: access cfg structure through DisasContext Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Philipp Tomsich | target/riscv: access configuration through cfg_ptr... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Philipp Tomsich | target/riscv: riscv_tr_init_disas_context: copy pointer... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Philipp Tomsich | target/riscv: refactor (anonymous struct) RISCVCPU... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Frédéric Pétrot | target/riscv: correct "code should not be reached"... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Petr Tesarik | Allow setting up to 8 bytes with the generic loader Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-02-16 | Wilfred Mallawa | include: hw: remove ibex_plic.h Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Relax UXL field for debugging Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Enable uxl field write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Set default XLEN for hypervisor Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust scalar reg in vector with XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust vector address with mask Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Fix check range for first fault only Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Remove VILL field in VTYPE Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust vsetvl according to XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Split out the vill from vtype Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Split pm_enabled into mask and base Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Calculate address according to XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Alloc tcg global for cur_pm[mask|base] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Create current pm fields in env Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust csr write mask with XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Relax debug check for pm write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Use gdb xml according to max mxlen Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Extend pc for runtime pc write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Ignore the pc bits above XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Create xl field in env Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Sign extend pc for different XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Sign extend link reg for jal and jalr Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Don't save pc when exception return Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust pmpcfg access with mxl Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Anup Patel | roms/opensbi: Remove ELF images Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Anup Patel | hw/riscv: Remove macros for ELF BIOS image names Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Anup Patel | hw/riscv: spike: Allow using binary firmware as bios Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Allow Zve32f extension to be... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for narrowing... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for widening... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for single... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for scalar... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for configuration... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Allow Zve64f extension to be... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for narrowing... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for widening... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for single... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for scalar... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for vsmul... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for vmulh... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for load... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for configuration... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yanan Wang | softmmu/device_tree: Remove redundant pointer assignment Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Thomas Huth | softmmu/device_tree: Silence compiler warning with... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: enable riscv kvm accel Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Support virtual time context synchronization Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Implement virtual time adjusting with... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Add kvm_riscv_get/put_regs_timer Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Add host cpu type Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Handle KVM_EXIT_RISCV_SBI exit Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Support setting external interrupt by KVM Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Support start kernel directly by KVM Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Implement kvm_arch_put_registers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Implement kvm_arch_get_registers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Implement function kvm_arch_init_vcpu Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Add target/riscv/kvm.c to place the public... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | update-linux-headers: Add asm-riscv/kvm.h Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Wilfred Mallawa | hw: timer: ibex_timer: update/add reg address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Wilfred Mallawa | riscv: opentitan: fixup plic stride len Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Wilfred Mallawa | hw: timer: ibex_timer: Fixup reading w/o register Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | target/riscv: Implement the stval/mtval illegal instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | target/riscv: Fixup setting GVA Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | target/riscv: Set the opcode in DisasContext Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: actual functions to realize crs 128-bit... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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