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| 2023-01-06 | Richard Henderson | tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Richard Henderson | tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | LIU Zhiwei | target/riscv: Fix PMP propagation for tlb Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Alistair Francis | target/riscv: pmp: Fixup TLB size calculation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Jim Shu | hw/intc: sifive_plic: change interrupt priority register... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Jim Shu | hw/intc: sifive_plic: fix hard-coded max priority level Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Yang Liu | disas/riscv.c: rvv: Add disas support for vector instructions Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Sunil V L | hw/riscv: virt: Enable booting S-mode firmware from... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Sunil V L | hw/riscv: virt: Move create_fw_cfg() prior to loading... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Sunil V L | hw/arm, loongarch: Move load_image_to_fw_cfg() to common... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Wilfred Mallawa | hw/ssi: ibex_spi: fixup/add rw1c functionality Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Wilfred Mallawa | hw/ssi: ibex_spi: fixup coverity issue Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Bin Meng | hw/riscv: Update comment for qtest check in riscv_find_firmw... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Yang Liu | target/riscv: rvv-1.0: vf[w]redsum distinguish between... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Yang Liu | target/riscv: rvv-1.0: Simplify vfwredsum code Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Add initial support of type 6... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Check VU/VS modes for type 2 trigger Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Create common trigger actions... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Introduce tinfo CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Restrict the range of tselect... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Introduce tdata1, tdata2, and... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Introduce build_tdata1() to build... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Determine the trigger type from... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Bernhard Beschow | hw/riscv/sifive_e: Fix inheritance of SiFiveEState Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Frank Chang | target/riscv: Check the correct exception cause in... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Alistair Francis | hw/riscv: opentitan: Expose the resetvec as a SoC property Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Alistair Francis | hw/riscv: opentitan: Fixup resetvec Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Alistair Francis | target/riscv: Set the CPU resetvec directly Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Andrew Burgess | target/riscv: remove fixed numbering from GDB xml feature... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Andrew Burgess | target/riscv: remove fflags, frm, and fcsr from riscv... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Weiwei Li | target/riscv: fix csr check for cycle{h}, instret{h... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Rahul Pathak | target/riscv: Remove sideleg and sedeleg Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Alex Bennée | docs/system: clean up code escape for riscv virt platform Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Wilfred Mallawa | hw/ssi: ibex_spi: update reg addr Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-26 | Wilfred Mallawa | hw/ssi: ibex_spi: fixup typos in ibex_spi_host Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Atish Patra | target/riscv: Update the privilege field for sscofpmf... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Atish Patra | hw/riscv: virt: Add PMU DT node to the device tree Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Atish Patra | target/riscv: Add few cache related PMU events Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Atish Patra | target/riscv: Simplify counter predicate function Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Atish Patra | target/riscv: Add sscofpmf extension support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Atish Patra | target/riscv: Add vstimecmp support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Atish Patra | target/riscv: Add stimecmp support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Atish Patra | hw/intc: Move mtimer/mtimecmp to aclint Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Anup Patel | target/riscv: Use official extension names for AIA... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Rahul Pathak | target/riscv: Add xicondops in ISA entry Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Conor Dooley | hw/core: fix platform bus node name Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Conor Dooley | hw/riscv: virt: fix syscon subnode paths Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Conor Dooley | hw/riscv: virt: fix the plic's address cells Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Conor Dooley | hw/riscv: virt: fix uart node name Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Atish Patra | target/riscv: Remove additional priv version check... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Conor Dooley | hw/riscv: microchip_pfsoc: fix kernel panics due to... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Wilfred Mallawa | hw/riscv: opentitan: bump opentitan version Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Weiwei Li | target/riscv: Fix priority of csr related check in... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Daniel Henrique... | hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() Cc: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Dao Lu | target/riscv: Add Zihintpause support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | eopXD | target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Yueh-Ting (eop)... | target/riscv: rvv: Add mask agnostic for vector permutation... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Yueh-Ting (eop)... | target/riscv: rvv: Add mask agnostic for vector mask... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Yueh-Ting (eop)... | target/riscv: rvv: Add mask agnostic for vector floating... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Yueh-Ting (eop)... | target/riscv: rvv: Add mask agnostic for vector fix... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Yueh-Ting (eop)... | target/riscv: rvv: Add mask agnostic for vector integer... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Yueh-Ting (eop)... | target/riscv: rvv: Add mask agnostic for vector integer... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Yueh-Ting (eop)... | target/riscv: rvv: Add mask agnostic for vx instructions Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Yueh-Ting (eop)... | target/riscv: rvv: Add mask agnostic for vector load... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Yueh-Ting (eop)... | target/riscv: rvv: Add mask agnostic for vv instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Bin Meng | docs: List kvm as a supported accelerator on RISC-V Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Alexey Baturo | target/riscv: Fix typo and restore Pointer Masking... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Bin Meng | roms/opensbi: Upgrade from v1.0 to v1.1 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Weiwei Li | target/riscv: Simplify the check in hmode to reuse... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Weiwei Li | target/riscv: Fix checks in hmode/hmode32 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Weiwei Li | target/riscv: Add check for csrs existed with U extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Weiwei Li | target/riscv: Fix checkpatch warning may triggered... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Weiwei Li | target/riscv: H extension depends on I extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Weiwei Li | target/riscv: Add check for supported privilege mode... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Jason A. Donenfeld | hw/riscv: virt: pass random seed to fdt Cc: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Weiwei Li | target/riscv: move zmmul out of the experimental properties Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Frédéric Pétrot | target/riscv: fix shifts shamt value for rv128c Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Anup Patel | target/riscv: Force disable extensions if priv spec... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-07 | Anup Patel | target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-08-01 | Richard Henderson | linux-user/riscv: Align signal frame to 16 bytes Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-27 | Atish Patra | hw/intc: sifive_plic: Fix multi-socket plic configuraiton Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-27 | Palmer Dabbelt | RISC-V: Allow both Zmmul and M Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Anup Patel | target/riscv: Update default priority table for local... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Anup Patel | target/riscv: Remove CSRs that set/clear an IMSIC interrupt... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Anup Patel | target/riscv: Set minumum priv spec version for mcountinhibit Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Alistair Francis | hw/riscv: boot: Reduce FDT address alignment constraints Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Anup Patel | target/riscv: Don't force update priv spec version... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Alistair Francis | target/riscv: Ibex: Support priv version 1.11 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Alistair Francis | target/riscv: Fixup MSECCFG minimum priv check Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Atish Patra | target/riscv: Support mcycle/minstret write operation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Atish Patra | target/riscv: Add support for hpmcounters/hpmevents Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Atish Patra | target/riscv: Implement mcountinhibit CSR Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Atish Patra | target/riscv: pmu: Make number of counters configurable Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Atish Patra | target/riscv: pmu: Rename the counters extension to pmu Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Atish Patra | target/riscv: Implement PMU CSR predicate function... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Atish Patra | target/riscv: Fix PMU CSR predicate function Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Nicolas Pitre | target/riscv/pmp: guard against PMP ranges with a negative... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Richard Henderson | target/riscv: Minimize the calls to decode_save_opc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Richard Henderson | target/riscv: Remove generate_exception_mtval Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-07-03 | Richard Henderson | target/riscv: Set env->bins in gen_exception_illegal Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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