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target/arm: Correctly initialize MDCR_EL2.HPMN
2021-02-10
Bin Meng
target/ppc: Add E500 L2CSR0 write helper
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-02-10
Bin Meng
hw/net: fsl_etsec: Reverse the RCTRL.RSF logic
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-02-10
Bin Meng
hw/ppc: e500: Fill in correct <clock-frequency> for...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-02-10
Bin Meng
hw/ppc: e500: Use a macro for the platform clock frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-02-02
Bin Meng
hw/ssi: imx_spi: Correct tx and rx fifo endianness
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-02-02
Bin Meng
hw/ssi: imx_spi: Correct the burst length > 32 bit...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-02-02
Bin Meng
hw/ssi: imx_spi: Round up the burst length to be multiple...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-02-02
Bin Meng
hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-02-02
Bin Meng
hw/ssi: imx_spi: Use a macro for number of chip selects...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-25
Bin Meng
net: checksum: Introduce fine control over checksum...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-24
Bin Meng
hw/sd: sd.h: Cosmetic change of using spaces
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-24
Bin Meng
hw/sd: ssi-sd: Use macros for the dummy value and tokens...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-24
Bin Meng
hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-24
Bin Meng
hw/sd: ssi-sd: Add a state representing Nac
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-24
Bin Meng
hw/sd: ssi-sd: Suffix a data block with CRC16
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-24
Bin Meng
util: Add CRC16 (CCITT) calculation routines
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-24
Bin Meng
hw/sd: sd: Drop sd_crc16()
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-24
Bin Meng
hw/sd: sd: Support CMD59 for SPI mode
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-24
Bin Meng
hw/sd: ssi-sd: Fix incorrect card response sequence
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-16
Bin Meng
target/riscv: Remove built-in GDB XML files for CSRs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-16
Bin Meng
target/riscv: Generate the GDB XML file for CSR registers...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-16
Bin Meng
target/riscv: Add CSR name in the CSR function table
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-16
Bin Meng
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-16
Bin Meng
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-16
Bin Meng
hw/block: m25p80: Don't write to flash if write is...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-08
Bin Meng
docs/system: arm: Add sabrelite board description
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-08
Bin Meng
hw/arm: sabrelite: Connect the Ethernet PHY at address 6
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-08
Bin Meng
hw/msic: imx6_ccm: Correct register value for silicon...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2021-01-08
Bin Meng
hw/misc: imx6_ccm: Update PMU_MISC0 reset value
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-12-10
Bin Meng
target/i386: seg_helper: Correct segment selector nullificat...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-17
Bin Meng
hw/sd: Fix 2 GiB card CSD register values
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/riscv: microchip_pfsoc: Hook the I2C1 controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/riscv: microchip_pfsoc: Correct DDR memory map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/riscv: microchip_pfsoc: Map the reserved memory...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/riscv: microchip_pfsoc: Connect the SYSREG module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/misc: Add Microchip PolarFire SoC SYSREG module...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/riscv: microchip_pfsoc: Connect the IOSCB module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/misc: Add Microchip PolarFire SoC IOSCB module support
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/riscv: microchip_pfsoc: Connect DDR memory controller...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/misc: Add Microchip PolarFire SoC DDR Memory Controller...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-11-03
Bin Meng
hw/riscv: microchip_pfsoc: Document where to look at...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-10-26
Bin Meng
hw/sd/sdcard: Zero out function selection fields before...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-10-22
Bin Meng
hw/intc: Move sifive_plic.h to the include directory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Sort the Kconfig options in alphabetical...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Drop CONFIG_SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Always build riscv_hart.c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Move sifive_test model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Move sifive_uart model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Move riscv_htif model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Move sifive_plic model to hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Move sifive_clint model to hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Move sifive_gpio model to hw/gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Move sifive_u_otp model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Move sifive_u_prci model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Move sifive_e_prci model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: sifive_u: Connect a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: clint: Avoid using hard-coded timebase frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: microchip_pfsoc: Hook GPIO controllers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/net: cadence_gem: Add a new 'phy-addr' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: microchip_pfsoc: Connect a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/dma: Add SiFive platform DMA controller emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/sd: Add Cadence SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/char: Add Microchip PolarFire SoC MMUART emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: Initial support for Microchip PolarFire SoC...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
target/riscv: cpu: Set reset vector based on the configured...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
hw/riscv: hart: Add a new 'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-09-09
Bin Meng
target/riscv: cpu: Add a new 'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-08-22
Bin Meng
gitlab-ci/opensbi: Update GitLab CI to build generic...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-08-22
Bin Meng
hw/riscv: spike: Change the default bios to use generic...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-08-22
Bin Meng
hw/riscv: Use pre-built bios image of generic platform...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-08-22
Bin Meng
roms/Makefile: Build the generic platform for RISC...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-08-22
Bin Meng
roms/opensbi: Upgrade from v0.7 to v0.8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-08-22
Bin Meng
configure: Create symbolic links for pc-bios/*.elf...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-08-22
Bin Meng
hw/riscv: sifive_u: Add a dummy L2 cache controller...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-08-21
Bin Meng
hw/sd: Correct the maximum size of a Standard Capacity...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-08-21
Bin Meng
hw/sd: Fix incorrect populated function switch status...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-07-22
Bin Meng
hw/riscv: sifive_e: Correct debug block size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-07-14
Bin Meng
hw/riscv: Modify MROM size to end at 0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-07-14
Bin Meng
hw/riscv: virt: Sort the SoC memmap table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-07-14
Bin Meng
MAINTAINERS: Add an entry for OpenSBI firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_u: Add a dummy DDR memory controller...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_u: Sort the SoC memmap table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_u: Support different boot source per...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive: Change SiFive E/U CPU reset vector...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
target/riscv: Rename IBEX CPU init routine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_u: Add a new property msel for MSEL...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_u: Rename serial property get/set...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_u: Add reset functionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_gpio: Do not blindly trigger output...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_u: Hook a GPIO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_gpio: Add a new 'ngpio' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_gpio: Clean up the codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_u: Generate device tree node for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_u: Simplify the GEM IRQ connect code...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: opentitan: Remove the riscv_ prefix of the...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-19
Bin Meng
hw/riscv: sifive_e: Remove the riscv_ prefix of the...
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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