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| 2022-04-29 | Weiwei Li | target/riscv: rvk: add support for sha512 related instructio... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Weiwei Li | target/riscv: rvk: add support for sha256 related instructio... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Weiwei Li | target/riscv: rvk: add support for zkne/zknd extension... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Weiwei Li | target/riscv: rvk: add support for zknd/zkne extension... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Weiwei Li | crypto: move sm4_sbox from target/arm Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Weiwei Li | target/riscv: rvk: add support for zbkx extension Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Weiwei Li | target/riscv: rvk: add support for zbkc extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Weiwei Li | target/riscv: rvk: add support for zbkb extension Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Weiwei Li | target/riscv: rvk: add cfg properties for zbk* and zk* Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Frank Chang | target/riscv: Support configuarable marchid, mvendorid... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Bin Meng | hw/riscv: Don't add empty bootargs to device tree Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-29 | Bin Meng | hw/riscv: spike: Add '/chosen/stdout-path' in device... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Dylan Jhong | hw/riscv: boot: Support 64bit fdt address. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Bin Meng | hw/core: tcg-cpu-ops.h: Update comments of debug_check_watch... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Bin Meng | target/riscv: cpu: Enable native debug feature Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Bin Meng | target/riscv: machine: Add debug state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Bin Meng | target/riscv: csr: Hook debug CSR read/write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Bin Meng | target/riscv: cpu: Add a config option for native debug Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Bin Meng | target/riscv: debug: Implement debug related TCGCPUOps Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Jim Shu | hw/intc: riscv_aclint: Add reset function of ACLINT... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Frank Chang | hw/intc: Make RISC-V ACLINT mtime MMIO register writable Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Frank Chang | hw/intc: Support 32/64-bit mtimecmp and mtime accesses... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Frank Chang | hw/intc: Add .impl.[min|max]_access_size declaration... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Niklas Cassel | hw/riscv: virt: fix DT property mmu-type when CPU mmu... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Nicolas Pitre | target/riscv/pmp: fix NAPOT range computation overflow Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Ralf Ramsauer | hw/riscv: virt: Exit if the user provided -bios in... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Richard Henderson | target/riscv: Use cpu_loop_exit_restore directly from... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Weiwei Li | target/riscv: fix start byte for vmv<nf>r.v when vstart... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Atish Patra | target/riscv: Add isa extenstion strings to the device... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Tsukasa OI | target/riscv: misa to ISA string conversion fix Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Weiwei Li | target/riscv: optimize helper for vmv<nr>r.v Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Weiwei Li | target/riscv: optimize condition assign for scale < 0 Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Bin Meng | target/riscv: Add initial support for the Sdtrig extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Alistair Francis | target/riscv: Allow software access to MIP SEIP Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Alistair Francis | target/riscv: cpu: Fixup indentation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Atish Patra | target/riscv: Enable privileged spec version 1.12 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Atish Patra | target/riscv: Add *envcfg* CSRs support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Atish Patra | target/riscv: Add support for mconfigptr Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Atish Patra | target/riscv: Introduce privilege version field in... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Atish Patra | target/riscv: Add the privileged spec version 1.12.0 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Atish Patra | target/riscv: Define simpler privileged spec version... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Wilfred Mallawa | riscv: opentitan: Connect opentitan SPI Host Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-04-22 | Wilfred Mallawa | hw/ssi: Add Ibex SPI device model Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-31 | Yueh-Ting (eop)... | target/riscv: rvv: Add missing early exit condition... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-31 | Palmer Dabbelt | target/riscv: Avoid leaking "no translation" TLB entries Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Weiwei Li | target/riscv: expose zfinx, zdinx, zhinx{min} properties Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Weiwei Li | target/riscv: add support for zhinx/zhinxmin Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Weiwei Li | target/riscv: add support for zdinx Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Weiwei Li | target/riscv: add support for zfinx Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Weiwei Li | target/riscv: hardwire mstatus.FS to zero when enable... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Weiwei Li | target/riscv: add cfg properties for zfinx, zdinx and... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Wilfred Mallawa | hw: riscv: opentitan: fixup SPI addresses Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Anup Patel | hw/riscv: virt: Increase maximum number of allowed... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Anup Patel | docs/system: riscv: Document AIA options for virt machine Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Anup Patel | hw/riscv: virt: Add optional AIA IMSIC support to virt... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Anup Patel | hw/intc: Add RISC-V AIA IMSIC device emulation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Anup Patel | hw/riscv: virt: Add optional AIA APLIC support to virt... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-03-03 | Philipp Tomsich | target/riscv: fix inverted checks for ext_zb[abcs] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Yu Li | docs/system: riscv: Update description of CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Weiwei Li | target/riscv: add support for svpbmt extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Weiwei Li | target/riscv: add support for svinval extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Weiwei Li | target/riscv: add support for svnapot extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Weiwei Li | target/riscv: add PTE_A/PTE_D/PTE_U bits check for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Guo Ren | target/riscv: Ignore reserved bits in PTE for RV64 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | hw/intc: Add RISC-V AIA APLIC device emulation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Allow users to force enable AIA CSRs... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | hw/riscv: virt: Use AIA INTC compatible string when... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA IMSIC interface CSRs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA xiselect and xireg CSRs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA mtopi, stopi, and vstopi... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA interrupt filtering CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA hvictl and hviprioX CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA CSRs for 64 local interrupts... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA local interrupt priorities Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Allow AIA device emulation to set ireg... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Add defines for AIA CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Add AIA cpu feature Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Allow setting CPU feature from machine... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Improve delivery of guest external interrupts Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement hgeie and hgeip CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement SGEIP bit in hip and hie CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Anup Patel | target/riscv: Fix trap cause for RV32 HS-mode CSR access... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | LIU Zhiwei | target/riscv: Fix vill field write in vtype Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Philipp Tomsich | target/riscv: add a MAINTAINERS entry for XVentanaCondOps Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Philipp Tomsich | target/riscv: Add XVentanaCondOps custom extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Philipp Tomsich | target/riscv: iterate over a table of decoders Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Philipp Tomsich | target/riscv: access cfg structure through DisasContext Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Philipp Tomsich | target/riscv: access configuration through cfg_ptr... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Philipp Tomsich | target/riscv: riscv_tr_init_disas_context: copy pointer... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Philipp Tomsich | target/riscv: refactor (anonymous struct) RISCVCPU... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Frédéric Pétrot | target/riscv: correct "code should not be reached"... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Petr Tesarik | Allow setting up to 8 bytes with the generic loader Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-02-16 | Wilfred Mallawa | include: hw: remove ibex_plic.h Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-01-21 | LIU Zhiwei | target/riscv: Relax UXL field for debugging Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-01-21 | LIU Zhiwei | target/riscv: Enable uxl field write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-01-21 | LIU Zhiwei | target/riscv: Set default XLEN for hypervisor Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-01-21 | LIU Zhiwei | target/riscv: Adjust scalar reg in vector with XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-01-21 | LIU Zhiwei | target/riscv: Adjust vector address with mask Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-01-21 | LIU Zhiwei | target/riscv: Fix check range for first fault only Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-01-21 | LIU Zhiwei | target/riscv: Remove VILL field in VTYPE Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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