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qmiga/qemu.git
2021-12-20 Vineet Guptatarget/riscv: Enable bitmanip Zb[abcs] instructions
2021-12-20 Khem Rajriscv: Set 5.4 as minimum kernel version for riscv32
2021-12-20 Frank Changtarget/riscv: rvv-1.0: Add ELEN checks for widening...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: update opivv_vadc_check() comment
2021-12-20 Frank Changtarget/riscv: rvv-1.0: rename vmandnot.mm and vmornot...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: add vector unit-stride mask...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
2021-12-20 Frank Changtarget/riscv: rvv-1.0: add vsetivli instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point reciprocal estima...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point reciprocal square...
2021-12-20 Hsiangkai Wangtarget/riscv: gdb: support vector registers for rv64...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: trigger illegal instruction...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: implement vstart CSR
2021-12-20 Frank Changtarget/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing floating-point/integer...
2021-12-20 Frank Changtarget/riscv: add "set round to odd" rounding mode...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point/integer...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point/integer type...
2021-12-20 Frank Changtarget/riscv: introduce floating-point rounding mode...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point min/max instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove integer extract instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove vmford.vv and vmford.vf
2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove widening saturating scale...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width scaling shift instr...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point reductio...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width floating-point...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing fixed-point clip instr...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point slide instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: slide instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: mask-register logical instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point compare instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer comparison instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width saturating add...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening integer multiply-add...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing integer right shift...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer add-with-carry/subtract...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width bit shift instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width averaging add and...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer extension instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: whole register move instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point scalar move instr...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point move instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer scalar move instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: register gather instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: allow load element with sign...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: element index instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: iota instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: set-X-first mask bit instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: find-first-set mask bit instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: count population in mask instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point classify instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point square-root instr...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: take fractional LMUL into vector...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: update vext_max_elems() for...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: load/store whole register instru...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: fault-only-first unit stride...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: fix address index overflow bug...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: index load and store instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: stride load and store instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: configure instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove amo operations instructions
2021-12-20 Frank Changtarget/riscv: rvv:1.0: add translation-time nan-box...
2021-12-20 Frank Changtarget/riscv: introduce more imm value modes in transla...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: update check functions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: add VMA and VTA
2021-12-20 Frank Changtarget/riscv: rvv-1.0: add fractional LMUL
2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove MLEN calculations
2021-12-20 Frank Changtarget/riscv: rvv-1.0: check MSTATUS_VS when accessing...
2021-12-20 Greentime Hutarget/riscv: rvv-1.0: add vlenb register
2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add vcsr register
2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove rvv related codes from...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: add translation-time vector...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: introduce writable misa.v field
2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add sstatus VS field
2021-12-20 Frank Changtarget/riscv: rvv-1.0: set mstatus.SD bit if mstatus...
2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add mstatus VS field
2021-12-20 Frank Changtarget/riscv: Use FIELD_EX32() to extract wd field
2021-12-20 Frank Changtarget/riscv: drop vector 0.7.1 and add 1.0 support
2021-12-20 Frank Changtarget/riscv: zfh: add Zfhmin cpu property
2021-12-20 Frank Changtarget/riscv: zfh: implement zfhmin extension
2021-12-20 Frank Changtarget/riscv: zfh: add Zfh cpu property
2021-12-20 Kito Chengtarget/riscv: zfh: half-precision floating-point classify
2021-12-20 Kito Chengtarget/riscv: zfh: half-precision floating-point compare
2021-12-20 Kito Chengtarget/riscv: zfh: half-precision convert and move
2021-12-20 Kito Chengtarget/riscv: zfh: half-precision computational
2021-12-20 Kito Chengtarget/riscv: zfh: half-precision load and store
2021-12-20 Richard HendersonMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2021-12-18 Philippe Mathieu... hw/i386/vmmouse: Require 'i8042' property to be set
2021-12-18 Philippe Mathieu... tests/qtest/fuzz-megasas-test: Add test for GitLab...
2021-12-18 Philippe Mathieu... hw/scsi/megasas: Fails command if SGL buffer overflows
2021-12-18 Philippe Mathieu... hw/scsi: Fix scsi_bus_init_named() docstring
2021-12-18 Paolo Bonzinimeson: add "check" argument to run_command
2021-12-18 Paolo Bonzinicpu: remove unnecessary #ifdef CONFIG_TCG
2021-12-18 Paolo Bonzinimeson: reenable test-fdmon-epoll
2021-12-18 Paolo Bonziniconfigure: remove DIRS
2021-12-18 Paolo Bonziniconfigure: remove unnecessary symlinks
2021-12-18 Paolo Bonziniconfigure, meson: move ARCH to meson.build
2021-12-18 Paolo Bonzinimeson: rename "arch" variable
2021-12-18 Paolo Bonziniconfigure: unify x86_64 and x32
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